Generating a 600KHz clock with 10ps Jitter

[cksa]

You can't use a clock gen chip which supports down to 600kHz?

e.g. Si5348? https://www.silabs.com/documents/public/data-sheets/Si5348-D-DataSheet.pdf

[ali_asadzadeh]

You can't use a clock gen chip which supports down to 600kHz?

why?

[radiolistener]

FPGA has very high jitter. If you want low phase noise clock for ADC, you're needs to use external low phase noise oscillator and feed it directly to ADC clock input.

You can try to find 600 kHz quartz crystal and use it with with no PLL and no synthesizer to achieve low phase noise. But such crystal oscillator has significant temperature drift, so it may be worth to use some kind of oven to stabilize crystal temperature, like it is used in OCXO.

Also it may be worth to look for ultra low noise LDO as a power source for low phase noise oscillator.

Low phase noise is not so easy to achieve and it's not cheap, so it may cost you a lot of money, include solutions and test equipment.

[dietert1]

Kleinstein wrote above how to do it (the correct solution). You can use any high frequency low phase noise clock module and a single fast D-Type flipflop chip to sync. Clock generator and sync device should sit close to the ADC, that's how others have done it.

We don't know which ADC was going to be used and i am not saying that 10 ps or 100 ps clock jitter makes a difference when sampling at 600 KHz.

Regards, Dieter

[radiolistener]

i am not saying that 10 ps or 100 ps clock jitter makes a difference when sampling at 600 KHz.

Let's assume ADC is 20 bit and has 0.1 ps jitter, 0.41 LSB DNL, 0.9 LSB effective noise and we use 300 kHz signal on the ADC input, then

1) when oscillator has 10 ps jitter, we have 10.0005 ps combined jitter and 27.75 dB dynamic range degradation

2) when oscillator has 100 ps jitter, we have 100.00005 ps combined jitter and 47.67 dB dynamic range degradation

So, the difference between 10 ps jitter and 100 ps jitter will be about 47.67-27.75 = 19.92 dB.

Of course it will depends on ADC specifications.
For 16 bit ADC, the difference will be about 12.35 dB.
For 14 bit ADC, the difference will be about 3.42 dB.
For 12 bit ADC, the difference will be about 0.32 dB.

Also we don't know if topic starter planning to use undersampling. If yes, then the difference will be much higher.

[radiolistener]

and a single fast D-Type flipflop chip to sync

the jitter of fast D-type flipflop chip will be added to the oscillator jitter.

Logic gates have about the following jitter:
- 74LS00 - 4.95 ps
- 74HCT00 - 2.2 ps
- 74ACT00 - 0.99 ps
- LC100EL16 PECL - 0.7 ps
- NBSG16 Reduced Swing ECL (0.4V) - 0.2 ps

Since topic starter talking about 10 ps jitter, the jitter of the logic gate and self-jitter of ADC both needs to be taken into account.

[dietert1]

Certainly a 20 Bit ADC isn't of the flash type, but includes some kind of sample and hold, which will be affected by the states of other signals of the system, similar to logic timing inside a FPGA chip. I would guess acquisition at 20 bit accuracy is not possible within 1 nsec or less. Here we should be talking about a microsecond or so and i doubt that timing will be accurate to 0,1 psec. If i am wrong, i'd like to know what ADC we are discussing here.

Regards, Dieter

[radiolistener]

I would guess acquisition at 20 bit accuracy is not possible within 1 nsec or less. Here we should be talking about a microsecond or so and i doubt that timing will be accurate to 0,1 psec.

For the jitter, we're needs to take into account the frequency of the input signal. Don't confuse it with ADC clock frequency. My calculations above performed for 20 bit ADC working at 600 kHz sample rate. Since it is working at 600 kHz I assumed that the maximum input frequency is 300 kHz. So, for 300 kHz the difference in dynamic range between 10 ps and 100 ps jitter oscillator will be about 20 dB.

But the actual ADC bandwidth usually several times higher than the first Nyquist zone. Undersampling may be used to digitize input signal with much higher frequency. In such case the difference will be much higher.

So, there is needs to know the maximum frequency of the input signal, and ADC specifications.

[NorthGuy]

Kleinstein wrote above how to do it (the correct solution). You can use any high frequency low phase noise clock module and a single fast D-Type flipflop chip to sync.

That's how FPGA output is generated - fast D flops. They're already there, inside FPGA. You only need to clock them wisely.

[radiolistener]

They're already there, inside FPGA. You only need to clock them wisely.

The only problem with FPGA is that it has pretty high jitter. As I remember Cyclone 4 has about 100-200 ps jitter or even worse. So, you can't get 10 ps jitter on FPGA.

Even if you will use low phase noise oscillator with 0.1 ps jitter, if you wire it through FPGA, the combined jitter will be:

Tjrms-combined = sqrt(Tj-osc^2 + Tj-fpga^2 + Tj-adc^2) = sqrt(0.1^2 + 100^2 + 0.1^2) = 100.0001 ps

This is why you can't get lower jitter than the jitter of FPGA. Also you will needs to add jitter of the logic implemented in verilog for the clock. If you use PLL for that, you're needs to add PLL jitter, etc.

And this is why ADC with high dynamic range is clocked directly from oscillator and FPGA is not used to produce clock source for ADC.

[ali_asadzadeh]

Thanks radiolistener for the info , what's the jitter of Spartan 6 flip flops or the PPL output divide down by the internal logic?

[NorthGuy]

The only problem with FPGA is that it's gate has pretty high jitter. As I remember Cyclone 4 has about 100 ps jitter or something like that. So, you can't get 10 ps jitter on FPGA.

I guess by "gate" you mean input buffer. It certainly depends on the FPGA. Moreover, it is different depending on which pin you use and what input standard. I don't think FPGA would have worse input buffers than logic ICs.

Also you will needs to add jitter of the logic implemented in verilog for the clock.

The flop timing only depends on the clock, not on the data. If you clock your output flops with the original clock, then what happens in your logic doesn't really matter. What matters is only the clock which has very short travel:

Input buffer -> Clock buffer -> flop -> Output buffer

If you have 500 ps rise time at 3V, it is only 60 mV change during your 10 ps period. Any 60+ mV noise or variation in power level (such as not-ideal bypassing) will put you out of your 10 ps. If you have your low jitter at some point, it's very easy to lose it. I'd say keeping the clock inside FPGA may be better than using lots of traces, connections, vias etc.

Feeding the clock to FPGA is rather unusual design. Normally, you would feed clock to ADC, and ADC would provide a source-synchronous clock to FPGA to receive data. This way you have very short straight clock line. This would give you much better accuracy and lower jitter. If you need very low jitter, it's crazy to do otherwise.

However, if you do feed the clock to FPGA for some reason, I would expect that feeding ADC clock from FPGA outputs would give you somewhat better result compared to external divider.

[radiolistener]

what's the jitter of Spartan 6 flip flops or the PPL output divide down by the internal logic?

I don't know, needs to read datasheet. But I think it will not meet 10 ps requirement. Even fast 74 logic has about 5 ps. I think with Spartan 6 you will get something like 100-200 ps.

[radiolistener]

I don't think FPGA would have worse input buffers than logic ICs.

FPGA has much-much worse jitter for output buffers than fast 74 logic IC.
This is why fast logic IC is used to produce clock for ADC with high dynamic range. Just because if you wire clock through FPGA you will destroy high dynamic range by adding high jitter from FPGA.

That's the reason why FPGA never used to produce clock for jitter critical applications such as clock source for high dynamic range ADC.

Use FPGA to produce jitter critical clock is very bad idea. I think the best jitter you can get with FPGA is about 100 ps or something like that. For many applications critical to phase noise level this is not acceptable.

[radiolistener]

The flop timing only depends on the clock, not on the data.

The dynamic range of ADC depends on the frequency of the input signal and ADC clock jitter.
Just because clock jitter determines ADC aperture uncertainty. Aperture uncertainty leads to non-linear distortions and it reduces ADC SNR performance.

[NorthGuy]

FPGA has much-much worse jitter for output buffers than fast 74 logic IC.

Non-sense. Any datasheet reference?

The flop timing only depends on the clock, not on the data.

The dynamic range of ADC depends on the frequency of the input signal and ADC clock jitter.
Just because clock jitter determines ADC aperture uncertainty. Aperture uncertainty leads to non-linear distortions and it reduces ADC SNR performance.

What this has to do with anything, and how is it related to my sentence that you have quoted?

[radiolistener]

If you have 500 ps rise time at 3V, it is only 60 mV change during your 10 ps period.

If you put 300 kHz sine on the ADC input, on the 20 bit ADC you will get ideal SNR=122 dB.
But taking into account clock jitter and non linearity, in reality you will get:
- for 0 ps clock jitter: SNR = 111.5 dB
- for 1 ps clock jitter: SNR = 109.7 dB
- for 10 ps clock jitter: SNR = 94.4 dB
- for 100 ps clock jitter: SNR = 74.5 dB
- for 500 ps clock jitter: SNR = 60.5 dB
- for 1000 ps clock jitter: SNR = 54.5 dB

As you can see if you switch from 1 ps clock jitter to 500 ps clock jitter, you will lose 109.7 - 60.5 = 49.2 dB dynamic range.

49.2 dB equals to 8 bits.
So, you lose 8 bits of your ADC just because you're using ADC clock with 500 ps jitter instead of 1 ps.
This is actual for 300 kHz sine on the ADC input and don't depends on the clock frequency.

[radiolistener]

What this has to do with anything, and how is it related to my sentence that you have quoted?

ADC clock input needs low jitter to keep dynamic range according to specification.
ADC clock frequency doesn't matter. Jitter matters, not frequency.

Topic starter declared 10 ps jitter limit. This is impossible to achieve with FPGA.
At least with popular Cyclone 4 or Spartan 6 you will get about 100-200 ps for better case.

[radiolistener]

However, if you do feed the clock to FPGA for some reason, I would expect that feeding ADC clock from FPGA outputs would give you somewhat better result compared to external divider.

You're wrong. In practice DDC receiver which wire clock through FPGA has much worse dynamic range. You can see noise floor raising around carriers and typical high jitter behavior with reduced dynamic range.

When clock is wired directly to ADC (or through external high speed divider), the dynamic range is much better. Because clock with no FPGA has better jitter performance and it leads to better dynamic range.

You can use clock with jitter on digital domain, but analog signal should be captured with ADC clocked with low phase noise clock source. Low phase noise means low jitter.

Jitter leads to uncertainty of ADC aperture and it leads to higher noise. As result it leads to SNR degradation.


As you can see on the picture, it depends not only on the clock jitter, but also on the signal frequency on ADC input. Because different input signal frequency leads to different slew rate. The higher slew rate the higher noise will be produced for fixed jitter value.

[NorthGuy]

Topic starter declared 10 ps jitter limit.

Yes. That's digital signal. It has rise and fall times. It might be around 500 ps (50 times longer than 10 ps). Whatever samples this digital signal (presumably ADC, but it doesn't really matter) detects the clock edge every time when the signal passes through a certain threshold.

If the overall voltage level of the signal varies, the transition curve moves up and down.

When voltage rises, the curve moves up, so it will pass through the threshold earlier and the ADC will detect the clock edge earlier.

When voltage falls, the curve moves down, so it will pass through the threshold later and ADC will detect the clock edge later.

This is the mechanism which creates jitter (and adds this jitter to the pre-exosting jitter). Thus, if you don't control voltage variations, the jitter will become worse. This is primarily the question of stability of power supply, correct bypassing, PCB design etc. The more parts you add into your chain, the harder it is to control voltage variations and the worse jitter you are going to get.

Another factor is temperature. If it varies, the propagation delays change. Although this is a very slow change, it too depends on the number of components on the way of the signal.

This is impossible to achieve with FPGA.
At least with popular Cyclone 4 or Spartan 6 you will get about 100-200 ps for better case.

I don't think it's possible with anything.

However, there's no reason why 74 series ICs should be any different than FPGAs - they're built on the same technology and there's no reason to believe they would have dramatically different characteristics.

Although you probably cannot achieve 10 ps, you can try to do the best you can. If you use more components, more PCB traces, more legs, more vias etc., you will get more jitter because each of these elements can only add jitter, but cannot remove it. Thus the key is to use less of everything - straight PCB traces, good bypassing, less components, less things that can add jitter. In this respect, FPGA wins because everything is compact and you already have your signal inside FPGA.

[radiolistener]

Non-sense. Any datasheet reference?

You can find it in the "Cyclone IV Device Handbook":

Dedicated clock output period jitter: 300 ps

Regular I/O period jitter: 650 ps

[radiolistener]

I don't think it's possible with anything.

This is possible with low phase noise oscillator and high speed logic IC.

As I mentioned above, 74LS00 has jitter about 4.95 ps.

14 GHz D-flip-flop high speed IC has jitter specification about 2 ps.
More fast logic IC has 0.2 ps jitter.

ABRACON ultra low phase noise oscillators have maximum guaranteed 75 fs rms jitter over 12kHz to 20MHz BW.

As you can see, you can get 5 ps jitter with 74 series TTL logic.
Or 0.25 ps jitter with more fast high speed IC (not TTL, but RSECL or PECL).

This is at least 60 times better than you can get on dedicated clock output of FPGA and even 130 times better than regular FPGA I/O.

[NorthGuy]

Because clock with no FPGA has better jitter performance ...

That's what we're debating. If you stick "because" in front of it, it doesn't make it true. Clock which comes through FPGA will certainly gain some jitter. The clock which goes through the set of 74 logic ICs will gain some jitter too.

We're not debating the influence of the jitter on the ADC performance, and you're already posted 3 times about this.

[radiolistener]

Thus, if you don't control voltage variations, the jitter will become worse. This is primarily the question of stability of power supply, correct bypassing, PCB design etc. The more parts you add into your chain, the harder it is to control voltage variations and the worse jitter you are going to get.

yes, exactly. Low phase noise source requires low noise power supply and low jitter components.

[radiolistener]

However, there's no reason why 74 series ICs should be any different than FPGAs - they're built on the same technology and there's no reason to believe they would have dramatically different characteristics.

FPGA is an array of configurable gates. 74 series IC is a dedicated (non configurable) hardware circuit. This is much easier to layout simple and easy logic element on the crystal and optimize it for high speed and low jitter than do the same for a highly complicated and highly configurable array with high density of elements.

As I quoted Cyclone 4 datasheet above, FPGA has 300-650 ps jitter.
74HC series has about 4.95 ps jitter.

As you can see, 74HC has much-much better jitter performance than FPGA