Picking a "core frequency" for a FPGA

[SiliconWizard]

The above figures are interesting, but apart from that, I for one fail to really understand the OP's question.

What's a "core frequency" for a digital design? That doesn't really make sense. Your design may require a number of different clocks. And even if only one clock is required, or you derive all other clocks from a "master" clock, this master clock is not necessarily the highest frequency. Other clocks may be derived using PLLs and have higher frequencies. And anyway ultimately, the required clock frequencies completely depend on the design itself and its requirements. I don't see a point choosing an arbitrary frequency that would match all designs - that's just not possible in general, and I frankly don't see the point. Digital design is not software.

Besides, arbitrarily selecting some "highest common denominator" would just make your overall life harder, and ultimately draw a lot more power than required. Anyway.