Hi,
I'm developing a RMS module , input data are 24bit singed , here is the verilog code, But in model sim the results are wrong!?
what I have done wrong in the * operation?
module RMS (
//Interface
input i_Clk,
input i_Rst,
input signed [23:0] i_Data,
output reg [23:0] o_Data,
output reg o_Dv//output data valid
);
reg [47:0] r_MAC;
reg [7:0] r_SampleCnt;//it will count how many samples we got
wire [47:0] w_c;//to see the mul in debug window
always @(posedge i_Clk ) begin
if(i_Rst == 1'b1) begin
o_Data <= 24'h0;
r_MAC <= 48'h0;
r_SampleCnt <= 8'h0;
end else begin
o_Dv <= 1'b0;
r_MAC <= (i_Data * i_Data) + r_MAC;
r_SampleCnt <= r_SampleCnt + 1'b1;
if(r_SampleCnt == 8'hff) begin
o_Dv <= 1'b1;
end
end
end
assign w_c = i_Data*i_Data;
endmodule
The first input data is -668399 and the result should be 4467451921 But model sim shows a very big wrong number 446757223201