Author Topic: Why this simple code generates wrong results for MUL operation  (Read 1505 times)

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Offline ali_asadzadehTopic starter

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Why this simple code generates wrong results for MUL operation
« on: January 17, 2021, 11:09:31 am »
Hi,
I'm developing a RMS module , input data are 24bit singed , here is the verilog code, But in model sim the results are wrong!?
what I have done wrong in the * operation?

Code: [Select]

module RMS (
    //Interface
    input i_Clk,
    input i_Rst,
input signed [23:0] i_Data,
output reg [23:0] o_Data,
output reg o_Dv//output data valid
);

reg [47:0] r_MAC;
reg [7:0] r_SampleCnt;//it will count how many samples we got
wire [47:0] w_c;//to see the mul in debug window

always @(posedge i_Clk ) begin
if(i_Rst == 1'b1) begin
o_Data      <= 24'h0;
r_MAC       <= 48'h0;
r_SampleCnt <= 8'h0;
end else begin

o_Dv <= 1'b0;
r_MAC       <= (i_Data * i_Data) + r_MAC;
r_SampleCnt <= r_SampleCnt + 1'b1;

if(r_SampleCnt == 8'hff) begin
o_Dv <= 1'b1;
end
end

end

assign w_c = i_Data*i_Data;

endmodule

The first input data is -668399 and the result should be 4467451921‬  But model sim shows a very big wrong number 446757223201‬
« Last Edit: January 17, 2021, 01:47:26 pm by ali_asadzadeh »
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Offline tru

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Re: Why this simple code generates wrong results for MUL operation
« Reply #1 on: January 17, 2021, 12:13:07 pm »
I see that you have assigned i_Data with value: -668399, which is a lot bigger than you intended input: -66839.

Also a suggestion for the code:
Code: [Select]
o_Dv <= 1'b0;
...
if(r_SampleCnt == 8'hff) begin
o_Dv <= 1'b1;
end
to:
Code: [Select]
if(r_SampleCnt == 8'hff) begin
o_Dv <= 1'b1;
end
else begin
o_Dv <= 1'b0;
end
Reason is because the assignment operator <= is non-blocking and when the if statement is true, it is telling it to assign both values!
Although, it seems the compiler corrected your mistake so no errors in the simulation, no idea.
« Last Edit: January 17, 2021, 12:16:14 pm by tru »
 

Offline ali_asadzadehTopic starter

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Re: Why this simple code generates wrong results for MUL operation
« Reply #2 on: January 17, 2021, 01:46:43 pm »
Thanks for the points, Actually the first post value was correct in the picture and it can be fitted in a 24Bit value, I have corrected the first post value,

So any other Idea what might be wrong?
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Offline NorthGuy

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Re: Why this simple code generates wrong results for MUL operation
« Reply #3 on: January 17, 2021, 02:57:20 pm »
For what it's worth, 668399*668399=446757223201, unless my calculator is broken.
 

Online SiliconWizard

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Re: Why this simple code generates wrong results for MUL operation
« Reply #4 on: January 17, 2021, 03:09:20 pm »
For what it's worth, 668399*668399=446757223201, unless my calculator is broken.

Same here. There doesn't seem to be anything wrong with the op's code and sim result.

Looks like the op missed one digit and used 66839 instead of 668399.
 

Offline asmi

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Re: Why this simple code generates wrong results for MUL operation
« Reply #5 on: January 17, 2021, 04:06:35 pm »
Yep, here's what I got.

Offline asmi

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Re: Why this simple code generates wrong results for MUL operation
« Reply #6 on: January 17, 2021, 05:14:26 pm »
Reason is because the assignment operator <= is non-blocking and when the if statement is true, it is telling it to assign both values!
Although, it seems the compiler corrected your mistake so no errors in the simulation, no idea.
This is not a mistake, but a well-defined behavior. Multiple assignments are allowed, and only the last one in the code flow will actually take effect. This is very useful for assigning "default" values.
« Last Edit: January 17, 2021, 05:21:22 pm by asmi »
 

Offline ali_asadzadehTopic starter

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Re: Why this simple code generates wrong results for MUL operation
« Reply #7 on: January 17, 2021, 07:18:30 pm »
Thanks guys, my mistake on missing a digit on my calculator ;)
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