Gowin DSP, signed or unsigned? Or does it matter?

[asmi]

Even with 1 mm pitch BGAs, you can't use a reasonable drill/via size like 10 mil/24 mil.  I don't recall how small the vias have to be, but the bottom line is there are no BGA packages that allow the cheapest boards or part costs.  If nothing else the 1 mm pitch BGAs are high pin counts with correspondingly higher prices because of the longer testing time. 

10 mil is not reasonable - it's stone age technology at this point. See the JLCPCB ad at the top of the page - they can manufacture 4 layer boards with 3.5/3.5 mil and 0.25/0.4 mm vias for $7 per 5 boards! It doesn't get any cheaper than that! And you can get controlled impedance at no extra cost! Slightly higher "grade" fabs like WellPCB can go as low as 3/3 mils and 0.15/0.3 mm vias for a bit more money - about $40 per 5 boards, and they will manufacture custom stackup at no extra cost. I use them extensively for my 4 and 6 layer designs, so I have confidence in their quality and ability to deliver, even if they are not the fastest fab around.

Why do you think I don't look at data sheets?  That's how I know that Xilinx doesn't even make a part that will fit on my board unless i want to go with more expensive design rules.  It's 21.5 mm wide.  A QFP100 fits very well.  I guess I could use a QFP144 and wrap the pins around the board, soldered to the other side.

It's very obvious to anyone "in the know" that you didn't look, because if you did, you'd know that there are a lot of packages smaller than 21.5 mm. Smallest 1 mm pitch package is Spartan-7 in BGA-196 package, which is 15x15 mm and has 100 user IO pins, which is more than QFP100 and even QFP144. Not to mention that BGA packages provide far superior signal integrity for high-speed signals. Heck, take a look at the project linked in my signature - it uses that very S7 device, and drives 128Mx16 DDR2 memory, while still leaving almost entire IO bank (50 pins) for other connections. There are 13x13 packages with 0.8 mm pitch, which again can be broken out on cheap JLCPBC process.

If you want the absolute smallest package, take a look at Artix-7 in CP236/CP238 packages (10x10 mm). They are nominally 0.5 mm pitch, but their pinout (see attached pictures) is such that you can easily fully break it out on just two signal layers. You will need to "massage" the footprint a bit to get it to work with JLCPCB's 3.5 mil limit (using some other fab like WellPCB which can do 3 mil will make things much easier), but you can get up to 50K logic cells, and - the coolest part - 2 multi-gigabit transceivers capable of reaching up to 6.25 Gpbs each (depending on speed grade).

[gnuarm]

Even with 1 mm pitch BGAs, you can't use a reasonable drill/via size like 10 mil/24 mil.  I don't recall how small the vias have to be, but the bottom line is there are no BGA packages that allow the cheapest boards or part costs.  If nothing else the 1 mm pitch BGAs are high pin counts with correspondingly higher prices because of the longer testing time. 

10 mil is not reasonable - it's stone age technology at this point. See the JLCPCB ad at the top of the page - they can manufacture 4 layer boards with 3.5/3.5 mil and 0.25/0.4 mm vias for $7 per 5 boards! It doesn't get any cheaper than that! And you can get controlled impedance at no extra cost! Slightly higher "grade" fabs like WellPCB can go as low as 3/3 mils and 0.15/0.3 mm vias for a bit more money - about $40 per 5 boards, and they will manufacture custom stackup at no extra cost. I use them extensively for my 4 and 6 layer designs, so I have confidence in their quality and ability to deliver, even if they are not the fastest fab around.

0.25 mm IS 10 mil.  You can't route the fine pitch BGA parts using 10 mil via holes.  The last batch of boards I built had some $40+ worth of components and I only paid $60 to have built including assembly and test!  Even $5 per board pushes my costs up not to mention the cost of a large part vs. the smaller I/O count I need.  Add in the costs of adding extra layers to escape the BGA footprint and it mounts up quickly.

Why do you think I don't look at data sheets?  That's how I know that Xilinx doesn't even make a part that will fit on my board unless i want to go with more expensive design rules.  It's 21.5 mm wide.  A QFP100 fits very well.  I guess I could use a QFP144 and wrap the pins around the board, soldered to the other side.

It's very obvious to anyone "in the know" that you didn't look, because if you did, you'd know that there are a lot of packages smaller than 21.5 mm. Smallest 1 mm pitch package is Spartan-7 in BGA-196 package, which is 15x15 mm and has 100 user IO pins, which is more than QFP100 and even QFP144. Not to mention that BGA packages provide far superior signal integrity for high-speed signals. Heck, take a look at the project linked in my signature - it uses that very S7 device, and drives 128Mx16 DDR2 memory, while still leaving almost entire IO bank (50 pins) for other connections. There are 13x13 packages with 0.8 mm pitch, which again can be broken out on cheap JLCPBC process.

You seem to be getting angry about this.  As I have said repeatedly, the devices from Xilinx and Altera are either not low cost manufacturing friendly or just not LOW COST!  The Spartan-7 chip you are talking about is $15 compared to $4 from Gowin!!!  Not much comparison there. 

Clearly the designs you build are very different from the ones I typically build.  Please don't think that your needs are everyone's needs.

If you want the absolute smallest package, take a look at Artix-7 in CP236/CP238 packages (10x10 mm). They are nominally 0.5 mm pitch, but their pinout (see attached pictures) is such that you can easily fully break it out on just two signal layers. You will need to "massage" the footprint a bit to get it to work with JLCPCB's 3.5 mil limit (using some other fab like WellPCB which can do 3 mil will make things much easier), but you can get up to 50K logic cells, and - the coolest part - 2 multi-gigabit transceivers capable of reaching up to 6.25 Gpbs each (depending on speed grade).

I don't need 50 K whatever a logic cell is (a Xilinx marketing term with no hardware connection) or multi-gigabit transceivers.  The Artix-7 line starts at $25 for 8 KLUTs!!!  Compared to the Gowin parts at $4 for 9 kLUTs it's no contest!!!

It was actually Lattice that brought down the price of the high speed SERDES in FPGAs.  X and A were charging big bucks for their parts with SERDES and Lattice came out with a low cost line with them.  Then everyone else had to follow suit. 

[NorthGuy]

Not sure what you are trying to say.  The carry chain only handles the carry... hence the name.  Every adder and counter uses 1 LUT per bit whether they are 4 input or 6 input LUTs.

No. An adder requires two LUTs per bit - one LUT generates the result for this bit, the other LUT generates carry out.

You can, however, save some LUTs by combining consecutive bits. This way, to handle two consecutive bits you need three 5-input LUTs (4 bits from the operands and carry in). Since Xilinx's 6-input LUT can be reconfigured as two 5-input LUTs, you only need two LUTs to cover two consecutive bits for the adder. This is compared to two LUTs per bit if you only have 4-input LUTs. This is 2x savings even without carry chains.

If you use carry chains to calculate carry, you can completely eliminate the LUT which generates carry out. In the simplest form, you would have one 6-input LUT per bit which would be reconfigured as 2 5-input LUTs to produce the "generate" and "propagate" signals for the carry chain. So, it's one LUT per bit with 3 free inputs. In contrast, with 4-input LUTs, you would need two LUTs per bit, and only one free input.

What difference the free inputs in the LUTs make? A very big one. Because there's other logic. Say, you may want to mux what you're adding, or you may reset your counter to predefined values based on a number of conditions. You just feed extra signals to the free inputs of your LUTs and they take care of muxing, resetting etc. So, all or part of your logic gets absorbed by these LUTs.

What if you don't have free inputs in the LUTs? You need to designate other LUTs to all the muxing and resetting. Worse yet, these new LUTs will form a separate logic layer. Now you either need to pipeline or to take 40% speed hit because you now have two logic layers instead of one.

Are you suggesting they now have dedicated adder logic entirely separate from the LUTs to process the entire adder function?

This too. They have DSP blocks which do exactly this.

[gnuarm]

Not sure what you are trying to say.  The carry chain only handles the carry... hence the name.  Every adder and counter uses 1 LUT per bit whether they are 4 input or 6 input LUTs.

No. An adder requires two LUTs per bit - one LUT generates the result for this bit, the other LUT generates carry out.

I thought we were talking about FPGAs.  i don't know of any FPGA that doesn't provide logic to allow the carry chain to be optimized in some manner resulting in using 1 LUT per bit of adder/counter.  What parts are you talking about???

You can, however, save some LUTs by combining consecutive bits. This way, to handle two consecutive bits you need three 5-input LUTs (4 bits from the operands and carry in). Since Xilinx's 6-input LUT can be reconfigured as two 5-input LUTs, you only need two LUTs to cover two consecutive bits for the adder. This is compared to two LUTs per bit if you only have 4-input LUTs. This is 2x savings even without carry chains.

You mean it uses one LUT for each bit just like every other FPGA???  Ok, great... but zero advantage.

If you use carry chains to calculate carry, you can completely eliminate the LUT which generates carry out. In the simplest form, you would have one 6-input LUT per bit which would be reconfigured as 2 5-input LUTs to produce the "generate" and "propagate" signals for the carry chain. So, it's one LUT per bit with 3 free inputs. In contrast, with 4-input LUTs, you would need two LUTs per bit, and only one free input.

I don't know if you are speaking from knowledge of how this is done in the Xilinx 6 LUT parts or are speculating.  The whole thing above ignoring the carry chain applies to exactly zero FPGAs I am aware of except for one device Atmel made way back when.

What difference the free inputs in the LUTs make? A very big one. Because there's other logic. Say, you may want to mux what you're adding, or you may reset your counter to predefined values based on a number of conditions. You just feed extra signals to the free inputs of your LUTs and they take care of muxing, resetting etc. So, all or part of your logic gets absorbed by these LUTs.

What if you don't have free inputs in the LUTs? You need to designate other LUTs to all the muxing and resetting. Worse yet, these new LUTs will form a separate logic layer. Now you either need to pipeline or to take 40% speed hit because you now have two logic layers instead of one.

Yes, free inputs are useful *if* you have a use for them.  That's the point.  They initially used 4 input LUTs, not because there is an inherent restriction to 4 LUTs, but because they were found to give the optimal utility of logic and routing. 

The point is there is no basis for saying devices with 6 LUTs are X amount better than 4 LUTs.  Every design is different and has different requirements.  That's why some devices have 1 FF per LUT and others have fewer.  I believe in the case of these Xilinx parts (or at least some I've looked at) they have two registers per 6 LUT.  I suppose splitting LUTs let you use them more effectively. 

That doesn't change the fact that Xilinx has been using the "Logic Cell" equivalent number since long before they had 6 LUTs.  It's a marketing number with no real basis. 

Are you suggesting they now have dedicated adder logic entirely separate from the LUTs to process the entire adder function?

This too. They have DSP blocks which do exactly this.

We seem to be drifting far from any meaningful discussion.   If you like Xilinx that's fine.  I don't know why you are pushing them so hard.  The Gowin devices are what work for me in most of my designs.  They are exactly the company I have been hoping would appear for some time now.  It is very clear that Xilinx and Altera have no interest in the very high volume commodity market for smaller devices (smaller both in gate count and in package size).  Lattice has been working that ground for a while now and Gowin is hitting it hard.  If that's an area you don't work in, fine.  But it is exactly where I want to be.   

[NorthGuy]

If you like Xilinx that's fine.  I don't know why you are pushing them so hard.

I'm not trying to push anything. I'm trying to answer your questions. Why people like Xilinx, why 6-input LUTs are better than 4-input, how carry chain works, dedicated adders etc. etc. Looks like you know all this by yourself. But, for some reason, you don't let your knowledge to affect your evaluation of GOWIN products.

My original point, which I'm trying to carry, is that the GOWIN FPGA are not that cheap as you're trying to portray. Because of 2 factors:

- 6-input LUTs are substantially better than 4-input LUTs
- You're comparing DigiKey's prices for Xilinx chips to discounted prices for GOWIN

This is nothing wrong if GOWIN suits your needs. But it doesn't mean they're going to take over the world as you're trying to describe:

Only 4 or 9 kLUT and a price tag of $3 or $4.  Once people get over their aversion to using a product from a new company these parts will take off like a rocket!

[langwadt]

If you have an adder, it only needs a 4 input LUT per bit.  Unless you have other logic to combine with that the other 3/4 of the LUT is wasted as an example.  A counter only needs 3 inputs, etc.

Xilinx has built-in carry chains for adders and counters (4 carry cells in every CLB), or DSP blocks if you need long or fast. These things don't even count in the number of LUTs.

Not sure what you are trying to say.  The carry chain only handles the carry... hence the name.  Every adder and counter uses 1 LUT per bit whether they are 4 input or 6 input LUTs.  Are you suggesting they now have dedicated adder logic entirely separate from the LUTs to process the entire adder function?

I don't like BGAs because of the hassle of the ultra fine trace/space and vias required.

You can fan out 1mm pitch BGA with 6-8 mil traces. Doesn't sound like ultra fine to me.

We aren't talking about 1 mm pitch BGAs.  The parts available for the small Gowin devices are 0.5 or 0.4 mm pitch.  The whole point is to have a very small package to support mobile applications which is the high volume market for low end devices just like the 1,000 pin behemoths are for the high dollar/high profit telecomms and server markets which is where X and A are aligned.
Even with 1 mm pitch BGAs, you can't use a reasonable drill/via size like 10 mil/24 mil.  I don't recall how small the vias have to be, but the bottom line is there are no BGA packages that allow the cheapest boards or part costs.  If nothing else the 1 mm pitch BGAs are high pin counts with correspondingly higher prices because of the longer testing time. 

xilinx recommended pcb rules for ft256 1mm pitch is 12/23 mil via hole/size and 5/5 mill trace space, that is well with in JLCPCB dirt cheap capabilities

you can get  XC6SLX16-2FTG256C (14500 logic cells) for ~$5 on LCSC

[gnuarm]

If you like Xilinx that's fine.  I don't know why you are pushing them so hard.

I'm not trying to push anything. I'm trying to answer your questions. Why people like Xilinx, why 6-input LUTs are better than 4-input, how carry chain works, dedicated adders etc. etc. Looks like you know all this by yourself. But, for some reason, you don't let your knowledge to affect your evaluation of GOWIN products.

Wow!  You really insist on making this personal?! 

I have stated very, very clearly why I don't use Xilinx products on my boards.  Price is only a secondary issue.  The biggest one is package.  I don't recall who it was posted some misleading info on using BGAs in place of packages compatible with the low cost board fabrication I use.  Such devices all either require very small vias or have such a high I/O count they raise the price considerably where price does become a problem. 

No, you don't need to explain basic carry chains to me.  I believe it was you who started off talking about FPGAs needing two LUTs per bit for adders ignoring that virtually all FPGAs have adder logic built into every basic cell. 

Why are you going on like this?  Can we have a reasonable discussion?

My original point, which I'm trying to carry, is that the GOWIN FPGA are not that cheap as you're trying to portray. Because of 2 factors:

- 6-input LUTs are substantially better than 4-input LUTs
- You're comparing DigiKey's prices for Xilinx chips to discounted prices for GOWIN

I haven't heard any prices anyone else is getting from Xilinx...  I haven't asked for a quote because they don't make a part that will suit my boards.  Do you have such prices?  If not, please stop complaining that I'm comparing bogus prices.  Go to the Edge web page.  There you will find distributor prices very similar to what I've quoted.  Digikey doesn't carry them, so don't ask for that.

This is nothing wrong if GOWIN suits your needs. But it doesn't mean they're going to take over the world as you're trying to describe:

Only 4 or 9 kLUT and a price tag of $3 or $4.  Once people get over their aversion to using a product from a new company these parts will take off like a rocket!

LOL!  Ok, this trolley has reached city center in loony town.  Everybody off! 

I say the company will do well and you interpret that as my claiming Gowin will "take over the world". 

Please read my posts rather than just reacting to them.  Please. 

I said a couple of times that X and A are focused on the high end of the market where the telecomms pay big bucks for the biggest and fastest chips.  I know this because that is what Xilinx representatives have stated publicly in open forums.  That leaves the low prices, small packages end of the market to the innovative companies like Gowin.  Lattice has been a proponent of this segment and has some product lines that are doing well in it.  Gowin is doing an even better job and I expect them to be growing rapidly. 

If you think "growing rapidly" means they will take over the world, then you must have a pretty poor opinion of Xilinx's future. 

BTW, I bought a block of Xilinx stock a few months back and it is doing very well.  So obviously I'm neither forecasting nor hoping for Xilinx's doom.   I'd like to hold onto this for the gains to become long term capital gains, but the market may be heading for a tumble.  Pretty much anything can spook the herd at this point. 

[gnuarm]

If you have an adder, it only needs a 4 input LUT per bit.  Unless you have other logic to combine with that the other 3/4 of the LUT is wasted as an example.  A counter only needs 3 inputs, etc.

Xilinx has built-in carry chains for adders and counters (4 carry cells in every CLB), or DSP blocks if you need long or fast. These things don't even count in the number of LUTs.

Not sure what you are trying to say.  The carry chain only handles the carry... hence the name.  Every adder and counter uses 1 LUT per bit whether they are 4 input or 6 input LUTs.  Are you suggesting they now have dedicated adder logic entirely separate from the LUTs to process the entire adder function?

I don't like BGAs because of the hassle of the ultra fine trace/space and vias required.

You can fan out 1mm pitch BGA with 6-8 mil traces. Doesn't sound like ultra fine to me.

We aren't talking about 1 mm pitch BGAs.  The parts available for the small Gowin devices are 0.5 or 0.4 mm pitch.  The whole point is to have a very small package to support mobile applications which is the high volume market for low end devices just like the 1,000 pin behemoths are for the high dollar/high profit telecomms and server markets which is where X and A are aligned.
Even with 1 mm pitch BGAs, you can't use a reasonable drill/via size like 10 mil/24 mil.  I don't recall how small the vias have to be, but the bottom line is there are no BGA packages that allow the cheapest boards or part costs.  If nothing else the 1 mm pitch BGAs are high pin counts with correspondingly higher prices because of the longer testing time. 

xilinx recommended pcb rules for ft256 1mm pitch is 12/23 mil via hole/size and 5/5 mill trace space, that is well with in JLCPCB dirt cheap capabilities

you can get  XC6SLX16-2FTG256C (14500 logic cells) for ~$5 on LCSC

That's an interesting price.  I wonder why Digikey and Mouser and all the authorized distributors list prices five times that?  I don't know much about LCSC.  Do they buy from Xilinx do you know? 

Do you have a link for the Xilinx layout recommendations on using their BGAs?  I recall years ago I had a document that gave good info on that, but I haven't tried to track it down since then.  Or a document number should let me find it in a search.  At under $5 in quantity that would be a very useful chip and I'd like to investigate that. 

But I can't buy from second tier vendors.  My customers are large corporations that require all manner of certificates, RoHS, Reach, etc.  I don't see a sign that LCSC offers any of this.  Still, for some projects that's a very interesting price.  Thanks for the heads up.

[NorthGuy]

Do you have a link for the Xilinx layout recommendations on using their BGAs?  I recall years ago I had a document that gave good info on that, but I haven't tried to track it down since then.  Or a document number should let me find it in a search.

ug393 for Spartan-6, ug483 for 7-series

At under $5 in quantity that would be a very useful chip and I'd like to investigate that. 

See, when the price is right, the BGA/LUT considerations are suddenly not as important any more

[ejeffrey]

That's an interesting price.  I wonder why Digikey and Mouser and all the authorized distributors list prices five times that?  I don't know much about LCSC.  Do they buy from Xilinx do you know? 

The digikey/mouser prices are not what you pay for anything other than prototypes, especially with FPGAs.  You can see this because you can order 3rd party dev boards or SoMs for less than the digikey price of the bare chip.  They aren't selling those at a loss and the rest of the materials have non-zero cost.  We asked Intel for a quote for some mid-range Altera FPGAs and even in relatively small quantities got them for 1/3 the price.  IIRC, Intel didn't even sell them to us directly, the order was fulfilled by Arrow at 1/3 the list price.  These are much more expensive FPGAs than you are talking about so maybe you would need a larger quantity to get such a discount.  I don't know how LCSC gets their parts but it is not at all unbelievable that a Chinese distributor could have genuine parts at << the digikey price. 

[gnuarm]

Do you have a link for the Xilinx layout recommendations on using their BGAs?  I recall years ago I had a document that gave good info on that, but I haven't tried to track it down since then.  Or a document number should let me find it in a search.

ug393 for Spartan-6, ug483 for 7-series

At under $5 in quantity that would be a very useful chip and I'd like to investigate that. 

See, when the price is right, the BGA/LUT considerations are suddenly not as important any more

Thanks for the document number.  I don't  understand your statement about the package.  Of course the package is important.  The 256 pin package is the only possibly usable BGA in the Xilinx line up on my board because it fits (barely) and does not require the ultra small vias the other packages do. 

Even with that, it will be much harder to route this BGA than a 100 pin QFP because the vias are locked in place, with no option for moving them around to facilitate routing.  Fortunately in an FPGA there are not many I/Os that are fixed and the FPGA itself can be the routing resource to ease problems on the PCB.  So in the end it is still unlikely I will use the Xilinx part, but it is one of the choices I can consider. 

One of the problems I've had with pricing is that the quote is provided to me as the designing company.  I've never had a sales person explain how they can assure I will get that price through a contract manufacturer 10 years from now.  The board I have made millions of dollars on has been in production for over 12 years.  If I redesign it I will be setting up a means to manufacture it for another 12 years and need consistent pricing.

[gnuarm]

That's an interesting price.  I wonder why Digikey and Mouser and all the authorized distributors list prices five times that?  I don't know much about LCSC.  Do they buy from Xilinx do you know? 

The digikey/mouser prices are not what you pay for anything other than prototypes, especially with FPGAs.  You can see this because you can order 3rd party dev boards or SoMs for less than the digikey price of the bare chip.  They aren't selling those at a loss and the rest of the materials have non-zero cost.  We asked Intel for a quote for some mid-range Altera FPGAs and even in relatively small quantities got them for 1/3 the price.  IIRC, Intel didn't even sell them to us directly, the order was fulfilled by Arrow at 1/3 the list price.  These are much more expensive FPGAs than you are talking about so maybe you would need a larger quantity to get such a discount.  I don't know how LCSC gets their parts but it is not at all unbelievable that a Chinese distributor could have genuine parts at << the digikey price.

Of course Digikey 1 off prices are high.  My point is they are much higher for FPGAs than other devices and you have to negotiate with the manufacturer just to get an idea of pricing.  So when I see prices at Digikey or Mouser that are three times what I find for another product at another distributor, I assume they are not competitive in that race.

I don't know that LCSC is a Xilinx distributor.  Xilinx lists distributors on their web site and they don't list LCSC, hence my concern.   I don't want to use parts in my products that are grey market, potentially counterfeit.  So a $15 Xilinx part that is only listed at $5 on one Chinese web site, no, I'm not going to consider that a valid price until I find I can get a similar price through 1st tier distribution.

[langwadt]

One of the problems I've had with pricing is that the quote is provided to me as the designing company.  I've never had a sales person explain how they can assure I will get that price through a contract manufacturer 10 years from now.  The board I have made millions of dollars on has been in production for over 12 years.  If I redesign it I will be setting up a means to manufacture it for another 12 years and need consistent pricing.

they only way I see that you can get consistent pricing over such a long period is to buy all you need now, or someone else to buy all you need and sell it to you as you need them for a greatly increased price.

[gnuarm]

One of the problems I've had with pricing is that the quote is provided to me as the designing company.  I've never had a sales person explain how they can assure I will get that price through a contract manufacturer 10 years from now.  The board I have made millions of dollars on has been in production for over 12 years.  If I redesign it I will be setting up a means to manufacture it for another 12 years and need consistent pricing.

they only way I see that you can get consistent pricing over such a long period is to buy all you need now, or someone else to buy all you need and sell it to you as you need them for a greatly increased price.

That is simply not correct.  I have worked at companies where they get a quote from an FPGA maker and that price is honored for the life of the product, at least until the part is EOL.  Once they hand it off to Richardson all bets are off.   But you can still buy Spartan 3 devices from the 2003 time frame. 

My problem is that when I change contract manufacturers they have to jump through a bunch of hoops to connect my quote with the production run to get that price.  I typically don't have the time to mess with that.  The quote is connected to the product it was quoted for.  They don't want to give you a blanket quote to cover every app.  Sales is VERY motivated to push the newest line, much more so than just getting a design win.  So they don't want you to continue using their old product in your new designs.  They will give great quotes on the new line to get the wins.  Other lines get much less aggressive quotes.

[langwadt]

One of the problems I've had with pricing is that the quote is provided to me as the designing company.  I've never had a sales person explain how they can assure I will get that price through a contract manufacturer 10 years from now.  The board I have made millions of dollars on has been in production for over 12 years.  If I redesign it I will be setting up a means to manufacture it for another 12 years and need consistent pricing.

they only way I see that you can get consistent pricing over such a long period is to buy all you need now, or someone else to buy all you need and sell it to you as you need them for a greatly increased price.

That is simply not correct.  I have worked at companies where they get a quote from an FPGA maker and that price is honored for the life of the product, at least until the part is EOL.  Once they hand it off to Richardson all bets are off.   But you can still buy Spartan 3 devices from the 2003 time frame. 

My problem is that when I change contract manufacturers they have to jump through a bunch of hoops to connect my quote with the production run to get that price.  I typically don't have the time to mess with that.  The quote is connected to the product it was quoted for.  They don't want to give you a blanket quote to cover every app.  Sales is VERY motivated to push the newest line, much more so than just getting a design win.  So they don't want you to continue using their old product in your new designs.  They will give great quotes on the new line to get the wins.  Other lines get much less aggressive quotes.

so is that "aggressive quote" for a number of parts you buy now, or for any number of parts you may or may not buy over the next 12 years?

[gnuarm]

One of the problems I've had with pricing is that the quote is provided to me as the designing company.  I've never had a sales person explain how they can assure I will get that price through a contract manufacturer 10 years from now.  The board I have made millions of dollars on has been in production for over 12 years.  If I redesign it I will be setting up a means to manufacture it for another 12 years and need consistent pricing.

they only way I see that you can get consistent pricing over such a long period is to buy all you need now, or someone else to buy all you need and sell it to you as you need them for a greatly increased price.

That is simply not correct.  I have worked at companies where they get a quote from an FPGA maker and that price is honored for the life of the product, at least until the part is EOL.  Once they hand it off to Richardson all bets are off.   But you can still buy Spartan 3 devices from the 2003 time frame. 

My problem is that when I change contract manufacturers they have to jump through a bunch of hoops to connect my quote with the production run to get that price.  I typically don't have the time to mess with that.  The quote is connected to the product it was quoted for.  They don't want to give you a blanket quote to cover every app.  Sales is VERY motivated to push the newest line, much more so than just getting a design win.  So they don't want you to continue using their old product in your new designs.  They will give great quotes on the new line to get the wins.  Other lines get much less aggressive quotes.

so is that "aggressive quote" for a number of parts you buy now, or for any number of parts you may or may not buy over the next 12 years?

It is for every part bought for the product/program the quote was for.   I said that.  The vendor points you to the distributor with whom they provide the quote with.  I wasn't in purchasing, but I do recall my boss telling me they needed to be honest with them about which parts were being bought for which product line. 

In my business I got quotes for a few things I built, but when I started letting the CMs do the ordering they no longer honored the quotes they gave me.  They said they would have to look into it, but with the CM being in a different sales territory it required coordination with the sales  people in that area and I didn't have the time to mess with it.  I had to get product built.   So I gave up on that.  With the Gowin quotes I will buy the parts myself for the first few runs and get the pricing worked out with the CM after that.   At the prices they are quoting it will be worth it. 

I was looking at the jlcpcb capabilities and they have a lot of disconnects.  It is hard to tell what they really offer on the low cost service.  I used the chat and several times when I asked which set of specs they worked to (when there were conflicts) they said they would "adjust" the features to suit their process.  So at this point I don't know exactly what their capabilities really are. 

For example, on a 6 layer board they say
Min. drill size is 0.20mm
minimum via diameter is 0.45mm
annular ring size will be enlarged to 0.15mm in production
with a 0.2 mm hole and 0.15 mm annular ring that gives 0.5 mm via pad, not 0.45 mm. 

On the price sheet they talk about 0.45 mm via diameter or for more money they can do 0.2 mm holes and 0.4 mm via diameter.  This was when the guy in chat said they would round up the drill to what their process uses. 

Still, that might be ok.  The board I may modify uses 10 mil drill and 24 mil via pads.  As long as they assure the board meet IPC class II specs they can use whatever drill size they want.  I found where they have REACH, RoHS and other certificates, but I don't see any mention of IPC class ratings. 

I dug into the clearance section of their capabilities and I just can't crack the code.  They use the same drawing for three different specs, none off which are clear.  I really can't figure out just what I will get from them.  Too many mentions of XYZ "will be enlarged in production".

Do you use them for anything other than prototypes or one offs?

[NorthGuy]

Too many mentions of XYZ "will be enlarged in production".

If they say they're going to enlarge something, they will.

Here's an example.

In the design these were perfectly round 0.65 mm pads with 0.4 mm holes, which violated their 0.7 mm minimum size for pads. The design also violated their hole-to-hole rule of 0.5 mm (it was 0.4 mm since it's 0.8 mm between holes).

They enlarged the pads to 0.72 mm. This made the pads too close to each other, so they removed their edges leaving less than 0.1 mm between pads. This hugely violates their clearance rule. They also made holes slightly large but within tolerances - from 0.4 mm to 0.45 mm. This further violated the hole-to-hole rule, as it became 0.35 mm (comared to allowed 0.5 mm). But these violations didn't make any difference.

So, I think you should expect that they will enlarge/fix what they can even if this causes violations elsewhere. They will not fix what they cannot fix, and chances are that it'll come out Ok. Of course, if it doesn't come out Ok, the responsibility is yours.

[gnuarm]

Too many mentions of XYZ "will be enlarged in production".

If they say they're going to enlarge something, they will.

Here's an example.

In the design these were perfectly round 0.65 mm pads with 0.4 mm holes, which violated their 0.7 mm minimum size for pads. The design also violated their hole-to-hole rule of 0.5 mm (it was 0.4 mm since it's 0.8 mm between holes).

They enlarged the pads to 0.72 mm. This made the pads too close to each other, so they removed their edges leaving less than 0.1 mm between pads. This hugely violates their clearance rule. They also made holes slightly large but within tolerances - from 0.4 mm to 0.45 mm. This further violated the hole-to-hole rule, as it became 0.35 mm (comared to allowed 0.5 mm). But these violations didn't make any difference.

So, I think you should expect that they will enlarge/fix what they can even if this causes violations elsewhere. They will not fix what they cannot fix, and chances are that it'll come out Ok. Of course, if it doesn't come out Ok, the responsibility is yours.

That's my point.  While their capabilities provide for using 1.0 mm pitch BGAs potentially, their standard capabilities don't look like they will allow the use of 0.8 mm pitch BGAs.  Of course the devil is in the details and I find their rules to be too unclear to know exactly what they will and won't provide in the end.  The via/drill capability is a perfect example.  For the lower cost option they only provide a via size number and not a drill size.  So if I ask for a 10 mil (0.254 mm) drill and a 24 mil via pad (0.6 mm), what will I end up with?  Don't know.  If they take responsibility for giving me usable boards, fine.  If they churn out whatever they feel like after applying their ill defined capability rules, I can get very inexpensive dross that I can't use.  Then even inexpensive boards are expensive.

I expect I will only use JLC for even less demanding boards than I could get built most anywhere 12 years ago and find someone else for the boards I use in production.  Actually, I use a contract manufacturer who has their favorite board house as most do.  So I would only use an outfit like JLC for prototypes.  I'm really happy with this CM.  They not only build the boards, they test them and will drop ship to my customer.  Once they get rolling on a production run, I can just send the bills to my customer and wait for the checks.