EEVblog Electronics Community Forum
Electronics => FPGA => Topic started by: ali_asadzadeh on June 08, 2019, 09:06:40 am
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Hi,
I came across this Chinese FPGA manufacturer, the ARORA family seems nice
https://www.gowinsemi.com/en/product/detail/1/ (https://www.gowinsemi.com/en/product/detail/1/)
So I have contacted them and they are responsive till now. I want to replace the Spartan 6 parts with these new babies! ;) I want to know if anybody on this forum have any experience with them, though I'm missing the floating point FFT and general floating */%+- IP cores, and I really needed them. maybe there is some solution to that. beside that any idea about this company?
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Thanks, Do you have any Idea about this company?
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I want to replace the Spartan 6 parts with these new babies! ;)
Why? ::)
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Why? ::)
The guy's in Iran, the US threats are real.
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Looks like an advanced Lattice FPGAs. I bet there is a linkage.
Spartan6 is 6 input LUTs, so more efficient with resources and faster.
Important is how their GoWin EDA tools work..
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Why? ::)
They are about 5 times cheaper! :)
The guy's in Iran, the US threats are real.
Do not believe in media! I can get access to all the parts very easily and even cheaper than US and Europe people, because of my Chinese friends :)
Looks like an advanced Lattice FPGAs. I bet there is a linkage.
Spartan6 is 6 input LUTs, so more effective with resources and faster.
Important is how their GoWin EDA tools work..
I should evaluate them soon. the good point about them is the 20K LE and internal SDRAM and a bonus is the LQFP and QFN package!
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Lattice ECP5 similarity is claimed, yosys support in elaboration..
https://twitter.com/dhdezr73/status/1093336976399441920
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GOWIN EDA - almost identical look and feel with Lattice tools like IceCube2, Radiant.
Simple IDE with basic editor and project manager.
Synplify Pro is used for the synthesis.
Tried with an existing design and got similar resources used as with an ICE40LP.
Nice!
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So how easy is it to buy these chips? And how is the part availability for small quantities in the long run?
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They opened the European office (in UK..) 6 months back, so hopefully they will start selling soon :D
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Programmer HW: the FT232H (single channel version of the FT2232) has been recognized by the programming sw as a "GOWIN USB CABLE (FT2CH)".
Thus the programing hw in the original box is FT2232 based.
Now, we need the chips :)
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Programmer HW: the FT232H (single channel version of the FT2232) has been recognized by the programming sw as a "GOWIN USB CABLE (FT2CH)".
Thus the programing hw in the original box is FT2232 based.
Now, we need the chips :)
That's very good news. I have the digilnet adapter for xilinx, so it can be used in both places.
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Programmer HW: the FT232H (single channel version of the FT2232) has been recognized by the programming sw as a "GOWIN USB CABLE (FT2CH)".
Thus the programing hw in the original box is FT2232 based.
Now, we need the chips :)
I think LCSC carry them.
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Gowin's flash-based fpgas offer embedded PeudoSRAM. And they have so many package options !
One has to register to get any datasheets, though.
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I think with their strategy and hobby friendly packages and huge price difference like 10X lower in price, they would soon get a good total share of the market!
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Cheap??? Their GW1N products are generally 2x the price (LCSC vs Lattice online store) than comparable iCE40 chips.
And their CSBGA packages are also available from Lattice, so nothing more competitive.
forget about their LITTLEBEE family,Check their ARORA family, their GW2A-18 is 5USD, it's equivalent to XC6SLX25 part which is around 35USD and this puppy cost 5USD :D
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There is an interesting claim/rumor on this reddit thread: https://www.reddit.com/r/FPGA/comments/990nl9/has_anyone_had_any_experience_with_gowin_fpgas/. (https://www.reddit.com/r/FPGA/comments/990nl9/has_anyone_had_any_experience_with_gowin_fpgas/.)
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I looked into it more and it seems all their executives have worked for lattice before, so likely also a large chunk of their employees too. If I had to guess they probably license everything from lattice.
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As long as they sell cheaper, it worth it! it dose not matter where they came from, I ordered some samples from them, I think I would get my hands on them not long from now :D
Also if they steal some tech from lattice, it shows that lattice either did not pay their employee what they needed or satisfy them, or they are very weak as protecting their tech, either way it's their fault!
But maybe they have done something by themselves! they have internal SDRAM and I do not see any lattice part with internal SDRAM, and that's interesting for me, having the SDRAM inside the chip and save some space ;D
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FYI, Trenz has two GOWIN boards on their website.
Trenz is a UK FPGA board mfg, covering all FPGA brands that sell to the public (sorry, no QuickLogic).
The headquarter of Trenz is in Germany.
I bought this product for testing:
https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM
The YunYuan IDE works, did a simple project, but without using the SDRAM so far. It is not the fastest, fmax for my design was about 70 MHz for a RS232 receiver and FIFO with BRAM, and sigma delta audio output from the BRAM. Testing the SDRAM will be my next step.
Before this I tried to contact Gowin for the price of their chips, because I couldn't get them in any shop. They forwarded my request to a distributor, who wants to sell minimum 200 pieces. But meanwhile lcsc.com has them in stock, at least a few types. I asked for a part with integrated PSRAM instead of the standard version with SDRAM, but looks like there are only some engineering samples of it, at least when I asked a few months ago, and I couldn't get it from them. Maybe if a big company asks them, they will produce it, but might be better not to bet on it and use the parts with SDRAM, if you need it.
Price is about the same for similar Lattice parts with external SDRAM, but the integrated SDRAM of the Gowin parts will simplify board design a lot.
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Oh nice, thanks for the info.
Oh and did you get any ballpark prices for those 200 quantities?
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Thanks for sharing, I got price info for them it's 5USD for the TQFP144 pin version without SDRAM and around 6.5 USD for the version with Internal SDRAM.
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FYI, Trenz has two GOWIN boards on their website.
Trenz is a UK FPGA board mfg, covering all FPGA brands that sell to the public (sorry, no QuickLogic).
..The YunYuan IDE works, did a simple project, but without using the SDRAM so far. It is not the fastest, fmax for my design was about 70 MHz for a RS232 receiver and FIFO with BRAM, and sigma delta audio output from the BRAM. Testing the SDRAM will be my next step.
..
The picorv32 example did 65MHz max on the Arora, as I can remember, my conservative guess would be 45MHz with the sdram or maybe 50MHz with psram (pseudosram -> a dram with sram interface) when talking a 32bit MCU on the chip. Their current technology is 55nm, I bet they will go to an finer node soon or later (they are a fabless company)..
Interesting chips are the LittleBees in the "UV" version - single voltage, and nonvolatile configuration on-chip flash (no external bitstream flash is needed). Are they available??
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The price was $8.28 for 200 of the GW1NR-UV4QN88P part. And the distributor said he did me a favor, because even 200 pieces would be normally below minimum order quantity. I guess they are used to sell it to Chinese companies with probably more than a million pieces per product.
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Thanks for sharing, I got price info for them it's 5USD for the TQFP144 pin version without SDRAM and around 6.5 USD for the version with Internal SDRAM.
Based on what quantity? Tx!
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Based on what quantity? Tx!
Around 100 to 1K units, also I think the sample prices is the same too.
They are chinese non-US company, they usually charge very low, the volume is effective in more than 10K units I believe, under 10K everything is the same price, almost no matter the volume ;) Not to mention I could get samples for free ;D
Also I believe the price matters where you live :)
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Around 100 to 1K units, also I think the sample prices is the same too.
They are chinese non-US company, they usually charge very low, the volume is effective in more than 10K units I believe, under 10K everything is the same price, almost no matter the volume ;) Not to mention I could get samples for free ;D
Also I believe the price matters where you live :)
Did you get the quote from Gowin? I guess the distributor I got the prices from, makes a nice profit then :)
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Did you get the quote from Gowin? I guess the distributor I got the prices from, makes a nice profit then :)
It's from their distributor, try to change that, also they have a website with very similar prices that sells them.
see these links
https://www.edgeelectronics.com/fpga/gw2a-lv18lq144c7-i6/ (https://www.edgeelectronics.com/fpga/gw2a-lv18lq144c7-i6/)
https://www.edgeelectronics.com/fpga/gw2ar-lv18lq144c7-i6/ (https://www.edgeelectronics.com/fpga/gw2ar-lv18lq144c7-i6/)
The version that you want is around 4USD
https://www.edgeelectronics.com/fpga/gw1nr-uv4qn88c5-i4/ (https://www.edgeelectronics.com/fpga/gw1nr-uv4qn88c5-i4/)
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It's from their distributor, try to change that, also they have a website with very similar prices that sells them.
Did you discover the lead times for the various families of parts?
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The version that you want is around 4USD
https://www.edgeelectronics.com/fpga/gw1nr-uv4qn88c5-i4/ (https://www.edgeelectronics.com/fpga/gw1nr-uv4qn88c5-i4/)
No, this is the SDRAM version. The version I asked for was the GW1NR-UV4QN88P (note the additional P at the end), but this is unobtanium anyway. This might explain the difference. But thanks, for this price difference it is worth thinking about if I could do the same with SDRAM, and maybe some BRAM for caching.
BTW, they told me that the PSRAM version is using the W955D8MBYA memory inside, couldn't find this information in the Gowin datasheets. They sent me a preliminary Winbond datasheet of it, where it was called "x8 IO pSRAM". But it doesn't really have a classic SRAM interface. Looks like in the current datasheet (https://www.winbond.com/resource-files/W955D8MBYA_85C_PKG_datasheet_A01-001_20190605.pdf), with the same pinout and content, it is called "HyperRAM". I wish everything would be SRAM and fast, would be much easier. At least HyperRAM is simpler than the usual SDRAM interface, but it requires 12 clocks worst case from chip select to data out, if a refresh latency is required.
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I worked with PSRAM in past (xilinx<-> 48ball 75ns psram). The interface was standard SRAM, worked fine, the only restriction is the R/W cycles cannot be longer as some specified time because it is dram inside.
It could be the GOWIN is using FPGA chip stacked with a separate DRAM/PSRAM chip (piggybacked chips, pretty popular, ie the GD32F103 chips).
Look at the PSRAM module description in the FPGA's DS, as I can remember the interface is more complex than the actual psram's W955D8MBYA chip ball count.
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I have downloaded Their EDA and I'm taking a look at it, Also I got their License too, and have applied the gowin license, Unfortunately I can not find the place to add the gowin Synplifypro license (which I got from them too), I have emailed them, but I think their response time is about 24-48 hours, how did you apply the Synplifypro license?
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You have to set the LM_LICENSE_FILE environment variable, e.g. to C:\Gowin\gowin_Synplifypro_xx.lic, if you saved the licence file in the gowin directory under the name gowin_Synplifypro_xx.lic.
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You have to set the LM_LICENSE_FILE environment variable, e.g. to C:\Gowin\gowin_Synplifypro_xx.lic, if you saved the licence file in the gowin directory under the name gowin_Synplifypro_xx.lic.
Thanks! you saved me a few days ;)
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Am I doing it right? the Synplifypro produce the results so fast! almost like a compiler, under 10 seconds for the examples, or did Xilinx and altera did shit into their software ;D
Also what a beauty is the GW2AR with internal SDRAM ;D ;D and a nice price tag :) do we have altium libraries?
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I've been playing with the gowin software and so far my impressions are:
1. The place & route is really bad. I tested a simple 32 bit adder (fed by a shift register) which achieves a Fmax of only 280MHz on GW2AR. I then did some hand placement and got to a Fmax of 360MHz. The software P&R put registers all over the place and nowhere close to the adder. It looks like the FPGA itself is quite capable (assuming the timing characterization is accurate that is), almost comparable to Xilinx 7 series (which achieves 380MHz Fmax on the same circuit on Artix-7 with Vivado P&R, hand optimization could not improve it further).
2. The FPGA architecture is quite abnormal. Xilinx has had 6-input LUTs since 65nm but these are still on 4-input LUTs, which means (in theory) worse timings but better resource utilization. I had the impression that routing delay usually dominates so you want to pack as much logic into a LUT as possible which is why Xilinx went with 6-LUT very early. The other peculiarity is that the gowin FPGA seems to lack enough flipflops because my FFT core which uses a mostly correct balance of LUT/FF on 7 series uses twice as many flipflops in percentage as it does LUTs on the gowin FPGA. If you look at the device map you'll see 1 out of 4 CLBs have no flipflop (!!!)
Overall I think the most pressing issue is the crap software P&R. I can only get my FFT core up to 200MHz on the gowin device after many rounds of timing whack-a-mole. For shits I tried the gowin FFT ipcore and it only goes up to 90MHz :bullshit: and isn't even a full-rate streaming design .
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Also does anyone have some idea as to why this is a 55nm chip but runs at a 1.0V core voltage and still seems to be pretty fast? Same with the anlogic ones. Spartan 6 was 45nm and ran on 1.2V. What kind of process is this? Maybe something with thin gate oxide but still large feature size?
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I think 55ULP is the same as the 40nm ULP (interestingly the 55nm is not listed there):
https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm# (https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm#)
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I've been playing with the gowin software and so far my impressions are:
1. The place & route is really bad. I tested a simple 32 bit adder (fed by a shift register) which achieves a Fmax of only 280MHz on GW2AR. I then did some hand placement and got to a Fmax of 360MHz. The software P&R put registers all over the place and nowhere close to the adder. It looks like the FPGA itself is quite capable (assuming the timing characterization is accurate that is), almost comparable to Xilinx 7 series (which achieves 380MHz Fmax on the same circuit on Artix-7 with Vivado P&R, hand optimization could not improve it further).
2. The FPGA architecture is quite abnormal. Xilinx has had 6-input LUTs since 65nm but these are still on 4-input LUTs, which means (in theory) worse timings but better resource utilization. I had the impression that routing delay usually dominates so you want to pack as much logic into a LUT as possible which is why Xilinx went with 6-LUT very early. The other peculiarity is that the gowin FPGA seems to lack enough flipflops because my FFT core which uses a mostly correct balance of LUT/FF on 7 series uses twice as many flipflops in percentage as it does LUTs on the gowin FPGA. If you look at the device map you'll see 1 out of 4 CLBs have no flipflop (!!!)
Overall I think the most pressing issue is the crap software P&R. I can only get my FFT core up to 200MHz on the gowin device after many rounds of timing whack-a-mole. For shits I tried the gowin FFT ipcore and it only goes up to 90MHz :bullshit: and isn't even a full-rate streaming design .
That's cool, is your FFT core open source? ;)
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That's cool, is your FFT core open source? ;)
Yes it's under github user gabriel-tenma-white. Some things are still WIP, namely the large FFT in DRAM stuff.
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Thanks, Is this the link?
https://github.com/owocomm-0/fpga-fft
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Yes
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Not bad.
Just took a look at a few source files. There's something I find a little odd about your code style though. You use no or very few "process" constructs and write many assignments with "when rising_edge(xxx)" directly in the architecture's body instead. I guess it's equivalent in the end, but it looks odd. Any reason for this style?
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Not bad.
Just took a look at a few source files. There's something I find a little odd about your code style though. You use no or very few "process" constructs and write many assignments with "when rising_edge(xxx)" directly in the architecture's body instead. I guess it's equivalent in the end, but it looks odd. Any reason for this style?
Finally someone noticed my unusual VHDL coding style ^-^
The main reason is I prefer to think in terms of circuits rather than a series of operations like in programming. To me
a <= expression when condition and rising_edge(clk)
just means to create a flipflop fed by a combinational "expression", and with clock enable fed by "condition".
If you look at this code:
process(clk)
begin
if(rising_edge(clk)) then
if condition1 then
result <= func(a+x);
elsif condition2 then
result <= func(a+y);
end if;
end if;
end process;
It's ambiguous exactly what hardware it will generate; there will be a mux driven by a combinational function of condition1 and condition2, but it isn't clear if the mux will be before the adder, before func, or after func. There is also an implicit clock enable generated because "result" isn't assigned from all branches.
If I rewrite that snippet my way it would be:
muxXY <= x when condition1 else y;
sum1 <= a+muxXY;
result <= func(sum1) when (condition1 or condition2) and rising_edge(clk);
When you look at this code you can just visualize the circuit in your head, and you quickly realize you have a LONG combinational path of a mux feeding an adder feeding a combinational "func". You can also see that there are two paths, a data path and a clock enable path. The clock enable path is short and the data path is long, which you won't easily see with the process version. You can also more easily see exactly where your registers are this way and know what paths may be a timing problem before synthesis.
This style of coding and way of thinking was actually influenced by a professor at the university I went to; he always complained about computing science students in his class who design hardware as if they are writing code. His words were "when you write HDL you should imagine a circuit in your head, not an algorithm or a program".
I have just recently gotten into a habit of drawing a block diagram before writing any code, and by the time I actually write code it's simply a transcription of the diagram. Usually I will have a pretty good idea of how many LUTs a circuit will use before synthesizing it, and I can also design with specific FPGA primitives in mind like the SRL16 (an addressable shift register using 1/2 of a LUT). For example I had just finished designing and verifying an AXI skid buffer based on the SRL16 that uses about a half the number of LUTs compared to the Xilinx one and also fully registers all ports.
I would definitely recommend doing things this way if you are starting out with FPGA design; it should generalize well to verilog as well and you will be able to make designs running at 400MHz rather than <100MHz ;)
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Thanks for the detailed answer.
I get your point. I can't say I fully agree with it though (not feeling like exposing in details why now, and it would also be off-topic), but I get it.
Just a couple quick remarks then:
- The style is so unusual that it's bound to probably confuse colleagues if you're going to work in teams, and likewise, you're probably going to have a hard time convincing others to adopt your style;
- It may also confuse simulation tools, or at least make the simulations much less efficient (so: much slower);
- It may hinder optimization at the synthesis level, or possibly on the contrary make it way better. That I just don't know, but for the tools not "seeing" any process could possibly trigger uncommon behavior;
- It looks a lot less structured to me (that may be a bit subjective);
- You seem to consider the fact that inferred latches are not going to happen with your style. Alright. But there are simple ways to avoid them when using processes as well;
- As to the "order" or organization of logic blocks, I'm really not convinced it will really make any difference when using modern tools;
- And finally, even though making digital designers think about the hardware is a good thing generally speaking, I don't think they should "overthink" this either at all times. It's good to grasp the concepts and know how to use them, but OTOH thinking too close to the hardware all the time is not very scalable for more complex designs. Yes it can help when you're trying to optimize for speed... but complex digital design should not be conducted just like analog circuit design for instance, so I think you still have to know how and when to use more abstract constructs.
Just the way I see it.
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I'm not all that experienced with VHDL, but it does look a bit harder to read when you have the clock edge mixed into to the statement like that.
Don't think Verilog has any way of adding clock sensitivity mixed into a statement in a similar way, but i suppose you can get the same end result by stuffing each thing into its own mini"always" statements like this:
always @(posedge clk) if(condition1 || condition2) result <= condition1 ? func(a+x) : func(a+y);
Tho its a bit hard to read so spreading it out like in your example makes it a bit more readable:
assign mux = condition1 ? x : y;
assign sum = a + mux;
always @(posedge clk) if(condition1 || condition2) result <= sum;
It is a more compact way of writing it and does mirror the implementation better, but i still think its a bit hard to read when you are just trying to figure out what it does by looking at it. Maybe its a bit better than in VHDL because the clocked part is clearly visible due to needing a different type of statement (But that's probably just my personal taste). To be honest i think both VHDL and Verilog are not all that great of a language. I tend to use Verilog only because it looked slightly less terrible at the time, not because it would seam like an actually good language.
So yeah i tend to prefer writing more drawn out code like that in an futile attempt to make these HDL languages a bit more readable.
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I think I just prefer to see flipflops explicitly spelled out rather than defining some logic to "happen at the rising edge"; for example I would like a syntax like:
result <= DFF(clk) << sum;Which makes it more clear there is a flipflop/delay from sum to result, and could also allow more than one flipflop on one line:
result <= DFF(clk) << func(DFF(clk) << a, DFF(clk) << b);
The other major difference is that when you have if/case statements in a process it's as if entire blocks of code are swapped out depending on the condition, which I find unphysical and unintuitive. IMO you should only ever assign to a signal once; a signal assignment isn't like assigning a value to a variable but rather driving a signal onto a wire, therefore multiple drivers or "swapping out" drivers is unphysical (there are no tristate buffers inside an FPGA). Inside a VHDL process you *can* assign to a signal twice and the synthesizer will create intermediate signals for you. I have actually tried using "process" a few times and found it's too easy to create bugs this way. I prefer to see an error when there are multiple drivers on a signal.
In the dataflow syntax when you write:
mux1 <= a when condition else
b when condition2 else
c;
"mux1" is always driven, and it is the source of the signal that's being swapped with a mux rather than the assignment itself, which I find easier to visualize.
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Well in Verilog the usual way of making a latch is using an if statement, but it could be done without one:
assign mux = condition1 ? x : y;
assign sum = a + mux;
always @(posedge clk) result <= (condition1 || condition2) ? sum : result;
This should be more true to the actual implementation inside the FPGA (I think clocked latches are a D flip flop with a MUX that loops its output into input when its supposed to hold state), but i think this makes it even more difficult to read.I agree that HDl languages should be written with the underlying logic implementation in mind, but the way these languages don't seam to make for all that clear code when things are written strictly implementation oriented.
I thought Altium Designer did a nice move in this regard by introducing schematics to HDL in a way that actually works. Its a "language" that works well for describing digital logic as implemented in a clear easily readable way. Too bad they pulled the plug on that just as it was starting to show promise.
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If you look at this code:
process(clk)
begin
if(rising_edge(clk)) then
if condition1 then
result <= func(a+x);
elsif condition2 then
result <= func(a+y);
end if;
end if;
end process;
It's ambiguous exactly what hardware it will generate; there will be a mux driven by a combinational function of condition1 and condition2, but it isn't clear if the mux will be before the adder, before func, or after func. There is also an implicit clock enable generated because "result" isn't assigned from all branches.
Actually, it's not at all ambiguous. It is completely clear from the description.
First, the signal result is registered -- it is on the left-hand side of the assignments that are in the if rising_edge(clk) ... block.
Next, you've specified a mux for the assignment. That mux has three inputs, not two -- the third input is the previous value.
Last, the mux select is implemented with a priority encoder. condition1 and condition2 could both be true at the same time, but your code says that you want the assignment for the former to take precedence. Of course if neither are true then the previous value is assigned.
Whether the synthesis tool chooses to use the flip-flops' CE inputs or not depends on what makes the most sense to it. I've written code with a signal that I thought the synthesis tool would use as a clock enable, but nope. The logic on the D and CE inputs were not what I expected. But think about it. If the synthesis result is functionally correct, it doesn't matter how the logic is implemented. All that matters is if it works as intended (and meets timing).
That said: you are entirely correct when you write, you quickly realize you have a LONG combinational path of a mux feeding an adder feeding a combinational "func".
Everyone writing any HDL should realize that the right-hand-sides of assignments really are bunches of combinational logic. And that the "if" statement is part of that logic.
If I have concerns that the large amount of combinatorial logic in my synchronous processes are not correct, sometimes I'll use VHDL variables and split that logic so it's visible in simulation. (Also it can make for shorter lines and more readable code.) It ends up being like your intermediate concurrent signal assignments, only they're within the process.
You can also see that there are two paths, a data path and a clock enable path. The clock enable path is short and the data path is long, which you won't easily see with the process version. You can also more easily see exactly where your registers are this way and know what paths may be a timing problem before synthesis.
I suppose it's worth doing the experiment to see what logic is created by the two idioms, and whether one or the other is faster. That all may depend on the fabric.
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Today, these Little baby Dragons arrived to me at last! ;D ;)
(https://img.techpowerup.org/190828/20190828-120402.jpg)
What should I do with them!? ^-^ ^-^ ^-^
They are so Cute >:D
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Thanks blueskull :-+
Do you have Altium Lib's too? ;)
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New sipeed Tang Nano, preorder:
https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html (https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html)
GW1N-1-LV:1152 LUT4, 864 FF(Flip-Flop)
72K B-SRAM(bits); 96K user flash(bits); 1 PLL
Support a 5 inches 800*480 screen
Onboard JTAG Downloader
Not support for DSP
Small size, low cost
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It seems LCSC no longer carries GOWIN chips.
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The franchised GOWIN Distributors are listed here:
https://gowinsemi.com/en/about/distributor/ (https://gowinsemi.com/en/about/distributor/)
European Distributors below:
Russia
Website: http://vostok-24.ru (http://vostok-24.ru)
Website: www.icgamma.ru (http://www.icgamma.ru)
UK & Ireland
Website: https://www.epsglobal.com (https://www.epsglobal.com)
Belgium
Website: https://alcom.be (https://alcom.be)
Netherlands
Website: https://alcom.nl/ (https://alcom.nl/)
Israel
Website: http://www.eldis.co.il/ (http://www.eldis.co.il/)
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Based on what quantity? Tx!
Around 100 to 1K units, also I think the sample prices is the same too.
They are chinese non-US company, they usually charge very low, the volume is effective in more than 10K units I believe, under 10K everything is the same price, almost no matter the volume ;) Not to mention I could get samples for free ;D
Also I believe the price matters where you live :)
If by "where" you mean what country, I expect that is true. I've received quotes on several devices GW1N-4 and -9 in packages from 48QFN, 88QFN and 100QFP, all great! I think the -4 was $3-$4 and the -9 was more like $5. I'm working an open source ventilator project and this device is going to work well. It does make some of the team members worried. I guess they just can't handle anything that isn't X or A... I mean X or I. I've only used L over the last 12 years and am very happy with the results. I expect to be very happy with G now. I'm looking forward to seeing G show up at Digikey and Mouser.
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They're already stocked at Mouser:
https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h
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If 200 pcs is high for you, still on Altera / Xilinx no business for you on gowin
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They're already stocked at Mouser:
https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h
Wow, the prices at Mouser are a lot higher than the other Distis quoted. I know where to buy them when the time comes.
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Yes, but does the others sells just a few units for prototyping? (really interested if they do)
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Yes, you'll have to go though some qualification possibly. But if you want some parts I can get them for you. I'm using the GW1N-UV9LQ100C5/I4 on a project and am on their RADAR. I'll be ordering a few soon. If anyone would like some I can get extras.
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Here's a thought. I've been thinking for some time of producing an FPGA eval board and the Gowin devices seem just the ticket. What if I designed a blank board based on the design we are doing on a project I'm in and had them assembled? Would people be interested in buying either the bare board or the assembly?
I guess it would be something like the Trenz board with a programming FTDI chip (which is more expensive than the Gowin part, lol) and a DIP like pin out so you could use it as a module in your design.
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blueskull , Thanks for sharing :-+
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I just got myself a tang nano board. Managed to get the tools loaded and working - small problem - I can't figure out how to get the bitstream into flash so it works from power-up. I can load it into sram, but it disappears next power cycle.
Can someone tell me the magic incantation required to have it so that the device runs from power up?
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Double-click in the "Operation" column, select Access mode as "Embedded flash", operation to desired one (erase/program).
Make sure the cable's settings (Edit->Cable Settings-Cable) has 2.5 MHz for frequency.
There were different versions of the programming cables, but generic programmer tool by default sets the frequency of 2MHz that is incompatible with Tang Nano.
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Many thanks. The secret was the speed - yes it was set to 2MHz. Set to 2.5MHz - all good. I spun my wheels for about an hour and was thinking 'it's got to be something simple!', so I figured the forum was the place to go.
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I just got myself a tang nano board. Managed to get the tools loaded and working - small problem - I can't figure out how to get the bitstream into flash so it works from power-up. I can load it into sram, but it disappears next power cycle.
Can someone tell me the magic incantation required to have it so that the device runs from power up?
Glad you got the flash working. What did it do when you had the speed wrong? Did the programmer act happy and it just would not boot?
I think someone mentioned (possibly in another thread as I can't find it) exactly how the Tang Nano appears to the drivers. Is there a special driver required or does it show up like a serial port?
The Nano uses a 1K Gowin part which is missing some of the features available in the larger devices. It has no multipliers (DSP) and no Shadow SRAM which I think is what they call distributed RAM in other brands, the memory in the LUTs. While both of these are also missing in the 2K LUT part (which isn't suprising since the 2K LUT part is mostly missing itself) the Shadow SRAM is also missing from the 4K LUT part. You have to get a 9K LUT part to use the RAM in the LUTs. I find that rather odd. There are also differences in some functions depending on having the C revision or not. Seems C revisions are all they are shipping now, but that is somewhat recent and there is nothing in the part number to indicate this.
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There are also differences in some functions depending on having the C revision or not. Seems C revisions are all they are shipping now, but that is somewhat recent and there is nothing in the part number to indicate this.
C version has better PLL, that's what I've been told by Gowin FAE.
There was something else having to do with the BRAMs or the DSP. I checked the FAE email and he noted "We DO support Dual Port BSRAM with Revision C silicon of the GW1N-9/GW1NR-9/GW1NS-2/GW1NS-4 series" as well as saying C has faster speed grades. No mention of the PLL.
Still, what bugs me is the limited info on what the rev C features and lack of markings. At least they assure they are only shipping the rev C at this time. The trick is you need to know to select rev C in the tools to support the new features.
Also, I don't get the lack of LUT RAM in most devices. The -4 is shipping as rev C but the data sheet does not indicate it includes LUT RAM. Their info is not all that good, maybe it's an oversight in the docs. I don't see LUT RAM available for the -4 devices in the rev 1.9.7 tools, so they just don't have it in any device other than the -9. Fortunately the -9 is still very affordable. You don't save much downsizing to a -4 or even a -1 unless you are using many, many units, it won't matter much to use the -9.
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There was something else having to do with the BRAMs or the DSP. I checked the FAE email and he noted "We DO support Dual Port BSRAM with Revision C silicon of the GW1N-9/GW1NR-9/GW1NS-2/GW1NS-4 series" as well as saying C has faster speed grades. No mention of the PLL.
Interesting. It seems -C version for LittleBee is different than -C version for Arora. My parts of interest are GW2AR and GW2ANR.
One of my many complaints about Gowin is they don't make clear the many distinctions and the similarities between product lines. The two main product lines have many differences even in the cell structure and the other IP like the DSP and BRAMs. I guess it's not just the What that they don't make clear, but also the How/Why. What is the intent of each line exactly?
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I wonder how many employees are at Potato Semiconductor ;D
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IF they go open, the opportunities would be endless
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If Cadence gives me a free license or someone gives me a ported PDK for a low cost EDA tool, I can roll a GHz clock buffer in a few hours in an ancient 350nm process.
Dunno the EDA tool, but for the PDK would 130nm do ? SkyWater Open Source PDK (https://github.com/google/skywater-pdk) :-)
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I've been eye watering this for a while. Unfortunately it is still largely empty.
Standard cells are in external repositories (https://cs.opensource.google/skywater-pdk). They claim "it should be usable for doing test chips" (https://skywater-pdk.readthedocs.io/en/latest/status.html), and they already had a call for the first MPW (multi project wafer) (https://groups.google.com/g/skywater-pdk-announce/c/cdzfGCADDIU) back in November...
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FYI, Trenz has two GOWIN boards on their website.
Trenz is a UK FPGA board mfg, covering all FPGA brands that sell to the public (sorry, no QuickLogic).
I thought they were German, but no matter. What I didn't like is that on their web site the cost of shipping to the US is rather large. Digikey is selling the Gowin board at the same price with much more reasonable shipping.
Sum: €28.13*
Shipping costs: €56.11*
Total amount: €84.24
Funny, I can't find this at Digikey now. I wonder if this has anything to do with Gowin being labeled a CCMC (Communist Chinese Military Company) by the US government?
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Gowin also ceased selling their boards (and all parts) from their Chinese distributors, and this has been a while. Seems like they want to move to a direct sales system
I have not buy gowin recently, So where should we get the parts, ask them directly?
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That's how I got mine.
That's great, are you in china right now? Because I want them in china too. what was the part and the price?
I'm interested in GW2AR and GW2ANR in QFN88 package >:D
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Funny, I can't find this at Digikey now. I wonder if this has anything to do with Gowin being labeled a CCMC (Communist Chinese Military Company) by the US government?
Gowin also ceased selling their boards (and all parts) from their Chinese distributors, and this has been a while. Seems like they want to move to a direct sales system.
This is not a Gowin product, it's from Trenz and they still sell the boards through Mouser, at least Mouser lists it.
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Gowin also ceased selling their boards (and all parts) from their Chinese distributors, and this has been a while. Seems like they want to move to a direct sales system
I have not buy gowin recently, So where should we get the parts, ask them directly?
I don't know about Canada, but Gowin is sold through Edge and Rutronik in the US. I was just in touch with Rutronic last week, so I'm pretty sure they are still in the loop.
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They're already stocked at Mouser:
https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h (https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h)
The prices are ridiculous. For example the GW1NR-LV9QN88C6 costs $26.76 and minimum order quantity is 168 pieces, and not in stock:
https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D (https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D)
The same chip is used on the Sipeed Tang Nano 9K dev board, which you can get in single quantities for $17.84:
https://www.aliexpress.com/item/1005003810691048.html (https://www.aliexpress.com/item/1005003810691048.html)
And you get an USB port for programming and UART, HDMI connector, display connector etc. on top. I guess the other distributors sell the chip cheaper if I have a product later and buy more, but looks like for prototyping it on my own board, the only solution now for me is to buy these boards and desolder the FPGA (which needs only a few minutes with my hot air station) :-// Well, I ordered 2 of the boards, one for developing, and one for desoldering :)
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The prices are ridiculous. For example the GW1NR-LV9QN88C6 costs $26.76 and minimum order quantity is 168 pieces, and not in stock:
https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D (https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D)
The same chip is used on the Sipeed Tang Nano 9K dev board, which you can get in single quantities for $17.84:
https://www.aliexpress.com/item/1005003810691048.html (https://www.aliexpress.com/item/1005003810691048.html)
And you get an USB port for programming and UART, HDMI connector, display connector etc. on top. I guess the other distributors sell the chip cheaper if I have a product later and buy more, but looks like for prototyping it on my own board, the only solution now for me is to buy these boards and desolder the FPGA (which needs only a few minutes with my hot air station) :-// Well, I ordered 2 of the boards, one for developing, and one for desoldering :)
Hello,
I bought ten pieces of two types as sample (4 EURO for piece) with Rutronik Poland (they are official Gowin reseller in Poland).
Best Regards
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I bought ten pieces of two types as sample (4 EURO for piece) with Rutronik Poland (they are official Gowin reseller in Poland).
Thanks, sounds good. I will try to ask the distributors again if I get my design working with the Tang board, always better to use new chips instead of desoldering it.
Maybe it is company policy to make it difficult for small fishes to buy them with one click as usual, to avoid too many support questions? Pretty short sighted, because some of these small fishes could create the next big project.
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They're already stocked at Mouser:
https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h (https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h)
The prices are ridiculous. For example the GW1NR-LV9QN88C6 costs $26.76 and minimum order quantity is 168 pieces, and not in stock:
https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D (https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D)
This is a sign that Mouser doesn't stock this chip normally and it is a special order. This is a common occurence among distributors and also an indicator to not to use this chip in a design; it is likely not very popular and may become obsolete sooner than other chips.
Mouser has a whole bunch of GW1NR-LV9 variants in stock in different packages which you can buy in single quantities.
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Well, it is the same chip as the Tang Nano 9K uses, so should be pretty popular. The first 300 sold out in 3 days: https://twitter.com/SipeedIO/status/1483382248023805954 But maybe the others are sold even more.
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I'd be carefull with labelling chips as popular for the sole reason they are used on demo boards. Often the footprint isn't the most optimal one for a design. The 88 pin QFN fits the Tang Nano board well because it probably is the package with the most pins they can fit on the board without going for a BGA package. There is a reason Mouser doesn't carry it as a standard part!
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Nice news from the Sipeed Twitter:
The GW1NR-LV9 (used on the Sipeed Tango Nano 9k) is supported by the "new" Education Version V1.9.8.03 of the software:
https://twitter.com/SipeedIO/status/1493961811925737476 (https://twitter.com/SipeedIO/status/1493961811925737476)
Good News: No license required.
Bad News: Some minutes ago it was only available on the Chinese version of their website.
Really Good News: Yes, I have tried to run the full process on the Sipeed Tang Nano 9k examples, and the software really works.
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Contact Edge Electronics in the US for any of the Gowin devices or tools. Have them drop ship the parts to you to avoid extra Trump fees.
They are more aggressive than Mouser.
There are inexpensive Gowin tools on AliExpress as well to get you started for at least the Little Bee family. Suggest to source the official kits by Gowin.
Here is one contact at Edge:
R.ILY(at)edgeelectronics.com
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I ordered a Tang Nano 4K, the one with hard Cortex-M3. I'm looking through the documentation and doing some trial and error... did someone manage to get a working set of tools and some example going ?
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Hi. Yes - we purchased this kit when it was first released.
Review the following:
https://cn.dl.sipeed.com/shareURL/TANG
A great contact @ Sipeed for assistance:
zepan[at]sipeed.com
and
support[at]sipeed.com
You can use the EDU version of the toolchain from Gowin to program this kit.
Also suggest to review this kit for the learning / example IPs:
https://github.com/magicjellybeanfpga/MiniStar
If you have questions, will try to answer them but lately have been up to our eyeballs on OEM design rework due to semiconductor industry blues. Major industries will be impacted unless we release new versions of our widgets so that is currently priority #1 for our company. The GOWIN devices are very nice and learned a great deal as compared to the never ending toolchain blues of using the Lattice devices. You can source the Gowin parts at very competitive costs from Edge Electronics (USA) as compared to Mouser = $$$.
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Hi,
I used the SiPeed Tang Nano 4k board to learn how to use FPGAs.
With the educational software you can program both the FPGA and the embedded uC without any restrictions.
I was able to get the uC running, the embedded hyperram and the gowin analyzer software for debugging.
I see the missing integrated simulator environment as the only shortcoming.
I thought, that the integration of FPGA, uC and memory makes it ideal to emulate a gameboy cartridge. So I have implemented this in a hobby project.
Unfortunately I had to realize that the availability of the gowin components for hobbyists is not given, so I had to use the nano board.
All in all the nano 4K board is excellent to enter the world of FPGAs...
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They're already stocked at Mouser:
https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h (https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h)
The prices are ridiculous. For example the GW1NR-LV9QN88C6 costs $26.76 and minimum order quantity is 168 pieces, and not in stock:
https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D (https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1NR-LV9QN88C6-I5?qs=wnTfsH77Xs7buQ0%2F7AN%2FvQ%3D%3D)
The same chip is used on the Sipeed Tang Nano 9K dev board, which you can get in single quantities for $17.84:
https://www.aliexpress.com/item/1005003810691048.html (https://www.aliexpress.com/item/1005003810691048.html)
And you get an USB port for programming and UART, HDMI connector, display connector etc. on top. I guess the other distributors sell the chip cheaper if I have a product later and buy more, but looks like for prototyping it on my own board, the only solution now for me is to buy these boards and desolder the FPGA (which needs only a few minutes with my hot air station) :-// Well, I ordered 2 of the boards, one for developing, and one for desoldering :)
The GW1NR-LV9QN88C6 is $5.28 at qty 1 at Edge Electronics. But none in stock. I made it up to the page where I enter the credit card info.
https://www.edgeelectronics.com/fpga/gw1nr-lv9qn88c6-i5/# (https://www.edgeelectronics.com/fpga/gw1nr-lv9qn88c6-i5/#)
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The GW1NR-LV9QN88C6 is $5.28 at qty 1 at Edge Electronics. But none in stock. I made it up to the page where I enter the credit card info.
Umm -- why would you want to give them your credit card info when they don't have the chip in stock an do not even give a lead time?
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Email them - they will reply. Rob was our last contact. Our parts were shipped out of HK and directly to us in Canada to avoid the Trump taxes. BTW - we also ordered some kits that are listed on the Gowin website but not mentioned on Mouser nor Edge's website so whatever you see on the factory website, should be available to you through distribution. Just sharing our experience with Gowin..
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The GW1NR-LV9QN88C6 is $5.28 at qty 1 at Edge Electronics. But none in stock. I made it up to the page where I enter the credit card info.
Umm -- why would you want to give them your credit card info when they don't have the chip in stock an do not even give a lead time?
Edge is not Digikey. They are not set up for easy anonymous ordering. The web site is for making contact. I dealt with both Edge and Rutronik when working on an open source project. Both were very helpful.
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Edge is not Digikey. They are not set up for easy anonymous ordering.
At least they are set up to easily take your credit card details online. ;)
Anyway, glad if they work well for you as a supplier.