Electronics > FPGA

Gowin M3 CPU usage with FPGA fabric

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mon2:
Hi. Still learning but making some progress on the use of the Gowin / Efinix FPGA devices.

Q: How to transfer data to / from the embedded CPU and the FPGA fabric ?

Specifically, enabled the m3 hard CPU inside the Gowin GW1NS-LV4C device to which we enabled 16 GPIO pins during the instantiation. Now this block of 16 GPIO pins are exclusively locked to the M3 CPU (ie. the fpga fabric cannot access the same GPIO pins). Inside the Keil C code for the M3 CPU, we can perform a toggle of the GPIO pins which are binding to the hardware with the constraint file.

This is all working well. Our LEDs are blinking as they should.

Having a mental block on how to now transfer data bytes from the CPU side to the FPGA side (and vice versa) so that the FPGA fabric can assist on some critical timed state machines.

One crude idea is to use the same GPIO pins to output parallel data with sideband handshake lines -> the FPGA fabric state machine then captures this data to process. However, this idea will eat up quite a number of port pins on the FPGA package.

The flexibility of FPGA devices is amazing but with a steep learning curve. Welcome any suggestions. Thanks !

pcprogrammer:
My guess would be that the IO lines from the MCU are available as internal targets for the FPGA fabric.

The GPIO pins you mention, are these normally available for the FPGA or strictly available for the MCU?

Because if they are normally available for the FPGA one can imagine that the connection from the MCU to the GPIO pins is made via the FPGA fabric, and that it should be possible to route them into the logic to, without having to connect them to a GPIO pin first.

Edit1: I took a look at the manual and I think the ABP2 bus can be used to interface whit the FPGA. http://cdn.gowinsemi.com.cn/DS821E.pdf page 36

Edit2: On the next page there is this diagram, which shows several options on how to connect with the FPGA. The GPIO's can be used as I guessed. But it looks like it is also possible to extend onto the AHB bus. The big question of course is how.

mon2:
Thank you. On the same level of thinking and found the reference design for the CM1 processor (using that for testing on one kit and using CM3 on another which has a hard M3 micro) -> the reference C code (GMD / Keil) is showing an example of the AHB2_EXI.

So far, little or no documentation but in reviewing the source code, it appears they are chatting with a (fabric based?) custom widget called MULTIPLE. Not sure if we have the FPGA verilog code for this example but will hunt around. Our Gowin FAE is on vacation for another week.


--- Quote ---/* -------------------------- Multiple ---------------------------- */
//type definition
typedef struct
{
  __IO   uint32_t  MULTIPLIER;        /* Offset: 0x000 (R/W) [7:0] */
  __IO   uint32_t  MULTIPLICAND;      /* Offset: 0x004 (R/W) [7:0] */
  __IO   uint32_t  CMD;               /* Offset: 0x008 (R/W) [1:0] */
  __I    uint32_t  RESULT;            /* Offset: 0x00C (R/ ) [15:0] */
}MULTIPLE_TypeDef;

//base address
#define MULTIPLE_BASE   AHB_M1

//mapping
#define MULTIPLE        ((MULTIPLE_TypeDef   *) MULTIPLE_BASE)

//bit definition
#define MUL_MULTIPLIER      ((uint32_t) 0x000000FF)
#define MUL_MULTIPLICAND   ((uint32_t) 0x000000FF)
#define CMD_START               ((uint32_t) 0x00000001)
#define STATUS_FINISHED      ((uint32_t) 0x00000010)
#define MUL_RESULT            ((uint32_t) 0x0000FFFF)
/* -------------------------- Multiple ---------------------------- */
--- End quote ---

So if this AHB extension can chat with this fabric based IP, we should be able to something similar.

There is also some mention of dual port SRAM on the forum but not sure if we have seen sample projects in the Gowin SDK but will search. That should also be ok for our needs.

Thanks again!

up8051:
Maybe it will be helpful:
https://github.com/verilog-indeed/nano4k_ahb_led

mon2:
That is an EXCELLENT find ! Thank you. Not comfortable with VHDL but will study and see if we can expand this sample project for our needs.

Can the toolchain allow for a mix of VHDL & VERILOG source files to be used inside the same project ?

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