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GOWIN Semi FPGA - BRAM IP usage

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up8051:
Hi,
 I have Tang Nano module with Gowin FPGA GW1N-1-LV.
 In my project I would like to use "Semi Dual Port RAM".
I can generate IP (by IP generator) but I confused about signal names and where is write signal
[attach=1]
PORT A is for Write for B is for Read:

--- Code: ---component Gowin_SDPB
    port (
        dout: out std_logic_vector(7 downto 0);
        clka: in std_logic;
        cea: in std_logic;
        reseta: in std_logic;
        clkb: in std_logic;
        ceb: in std_logic;
        resetb: in std_logic;
        oce: in std_logic;
        ada: in std_logic_vector(8 downto 0);
        din: in std_logic_vector(7 downto 0);
        adb: in std_logic_vector(8 downto 0)
    );
end component;
--- End code ---

The figure suggests that the OCE signal is for Port A.
I would rather expect that a signal OCE is for Port B ( OCE = Ouput Chip Enable?)
But where is write signal for port A?

Does anyone use Gowin FPGA and  could give a hint ?

Regards,
up8051

mon2:
Hi.

1) the Tang Nano is fitted with the GW1N-1-LV - please note this p/n.

2) Section 3.3 details the attached document contains timing charts for this specific interface. Port A is for write data; Port B is for read data. Each port operates without the r/w signal.

up8051:
Thank you.
The document was very helpful, the problem has been solved.

I have another question.
I have left about 400 LUTs , 2 BRAM blocks and  all User Flash. I would like to implement some simple softcore CPU to operate the buttons and the display.
Can you recommend something simple and proven?

nctnico:
One of the Picoblaze portable clones might work: https://en.wikipedia.org/wiki/PicoBlaze

up8051:
pacoBlaze - last modification 14 years ago
copyBlaze - 5 years ago

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