Electronics > FPGA

Gowin Simulation

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ali_asadzadeh:
Hi,
I have made a board for GW2AR-LV18QN part, And every thing is working as expected and I have written  UART,SPI, PWM peripherals and have tested them successfully.

Now I want to use the IP cores, for example the FIFO one, The problem for now is how can I simulate my design with the Gowin IO cores, using Modelsim etc...

I have found a folder named simlib in the installation folder,

I wonder if anyone in here has done simulation with gowin IP on modelsim or another simulation software, is it possible? how?

Any tips would be highly appreciated.

ali_asadzadeh:
Does any body use Gowin FPGA's in here?
The tools generate a SDF file, can it be used for simulation? how?

Bassman59:

--- Quote from: ali_asadzadeh on June 25, 2020, 09:32:37 am ---Does any body use Gowin FPGA's in here?
The tools generate a SDF file, can it be used for simulation? how?

--- End quote ---

Assuming that Gowin is no different from any other FPGA vendor --

In addition to the SDF file, the Gowin tools should provide a VHDL or Verilog model of the design which replaces your RTL/behavioral code with primitives. So you bring the new model and the SDF into your simulation tool, which needs to be able to do such back-annotated simulation. You use the same test bench as with your original design.

ModelSim and Aldec can do such simulation. I think that ghdl can do it, too.

ali_asadzadeh:
thanks, Do you have any web link or tutorial on how to do it?

up8051:
Did you resolve problem with IP simulation?

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