Gowin Simulation

[ali_asadzadeh]

Hi,
I have made a board for GW2AR-LV18QN part, And every thing is working as expected and I have written  UART,SPI, PWM peripherals and have tested them successfully.

Now I want to use the IP cores, for example the FIFO one, The problem for now is how can I simulate my design with the Gowin IO cores, using Modelsim etc...

I have found a folder named simlib in the installation folder,

I wonder if anyone in here has done simulation with gowin IP on modelsim or another simulation software, is it possible? how?

Any tips would be highly appreciated.

[ali_asadzadeh]

Does any body use Gowin FPGA's in here?
The tools generate a SDF file, can it be used for simulation? how?

[Bassman59]

Does any body use Gowin FPGA's in here?
The tools generate a SDF file, can it be used for simulation? how?

Assuming that Gowin is no different from any other FPGA vendor --

In addition to the SDF file, the Gowin tools should provide a VHDL or Verilog model of the design which replaces your RTL/behavioral code with primitives. So you bring the new model and the SDF into your simulation tool, which needs to be able to do such back-annotated simulation. You use the same test bench as with your original design.

ModelSim and Aldec can do such simulation. I think that ghdl can do it, too.

[ali_asadzadeh]

thanks, Do you have any web link or tutorial on how to do it?

[up8051]

Did you resolve problem with IP simulation?

[FlyingDutch]

Hello,
there is short note about simulation for Gowin FPGA in this document:

https://www.gowinsemi.com/upload/database_doc/1/document/5bfcfcab42d1c.pdf?_file=database_doc%2F1%2Fdocument%2F5bfcfcab42d1c.pdf

See paragraph : 6.4 Simulation.

Best Regards

[ali_asadzadeh]

Thanks, But There is no such option in the tools, I'm using 1.9.7.01 Beta, and I think it's the latest version.

[Saa1206]

Wanna simulate Gowin's IP-blocks in, say, Mentor's ModelSim.
E.g. CPLD GW1N-UV1P5LQ100C6/I5 OSCO, described in UG286-1.9.1E Gowin Clock User Guide.pdf page 100/104 topic 6.1.5 OSCO
At %Gowin_DIR%\Gowin_V1.9.8.01\IDE\simlib\gw1n\prim_sim.v look for OSCO

Code: [Select]

//OSCO,for gw1n-2
//Fosc = 250M/FREQ_DIV
module OSCO (OSCOUT, OSCEN);
parameter  FREQ_DIV = 100; // 2~128,only even num
parameter  REGULATOR_EN = 1'b0;  //1'b0, Powered by VCC!; 1’b1: Powered by regulator（only UV/LV）.
output OSCOUT;
input OSCEN;

reg oscr;
realtime half_clk;

initial  begin
    oscr = 1'b0;
    half_clk = 2*FREQ_DIV;
end

assign OSCOUT = OSCEN ? oscr : 1'b1;

always
       begin
            #half_clk;
            oscr = 1'b1;    
            #half_clk;
            oscr = 1'b0;
       end

endmodule
But what are FREQ_DIV and REGULATOR_EN?!
And where is clock division?!

[ali_asadzadeh]

Saa1206 could you do any simulation with IP at all?

[Mecanix]

For the record. This will teach how to import the Gowin's precompiled libraries into ModelSim / QuestaSim and run simulations based on their IPcores. Tested yesterday with QuestaSim 2023 & Gowin Designer 1.9.9.01 (build71333).

https://youtu.be/2uUcYFE-3S8?t=393   

[mon2]

BTW, a new version of the Gowin IDE was released earlier this week.

[ali_asadzadeh]

For the record. This will teach how to import the Gowin's precompiled libraries into ModelSim / QuestaSim and run simulations based on their IPcores. Tested yesterday with QuestaSim 2023 & Gowin Designer 1.9.9.01 (build71333).

https://youtu.be/2uUcYFE-3S8?t=393   

Thanks for sharing