Electronics > FPGA

Gowin Vs. Yosys

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Rainwater:
Gowin (1) Yosys (0)

I have been trying to figure out why this design works in simulation but not on my device
I have been tracking down an off by one error "on-chip", that does not match simulations.
If I build and load the verilog with yosys and nextpnr, the error is present and the design broken.
If I build this with GOWIN's toolchain, the design works as expected.

anyone have any tips about this kind of problem?
If this is a bug in yosys, whats the proper way to report it?
Code can be found here
https://github.com/Adivinedude/UART-Echo-Service
Dev board tang nano 9k.

UART.fs - Yosys/nextpnr
GOWIN_UART.fs - Gowin toolchain

Please feel free to give coding pointers as well. every bit helps

iMo:

--- Quote from: Rainwater on March 21, 2024, 12:57:16 am ---..If this is a bug in yosys, whats the proper way to report it?
..

--- End quote ---

https://github.com/YosysHQ/yosys/issues

Gowin
https://github.com/YosysHQ/apicula
https://github.com/YosysHQ/apicula/issues

colorado.rob:
Apicula has many bugs. Report them as you find them.

Use Apicula if you want to help them chase down bugs and improve the tool.

Use Gowin if you need a tool that works.

pcprogrammer:
Don't forget that Apicula is the result of reverse engineering and not based on any proper manufacturers documentation. This simply because there is none available.

This makes it very likely that there are errors in both timing information as well as missing configuration bits that make or break something.

Also the reverse engineering will most likely have been done on older versions of the Gowin software and might not be up to date on already by Gowin solved bugs in their own software.

Rainwater:
Im just not sure if its a bug or inexperience.
Before I got my code this far, i spent a week chasing down why different modules where randomly resetting. (Directly using an external input is bad practice)
Then another few days figuring out why logic was randomly sampling just after clock edges and not before `always @( posedge clk)` instead of `always @(*)`
Im almost 90% sure this is something being inferred in a way I dont yet understand. This has been the reason for every misunderstanding me and yosys have had.
Ill send this their way, might be able to help them.

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