Electronics > FPGA

HDL code for positive edge triggered J-K flip-flop with preset and clear

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--- Quote from: SiliconWizard on June 09, 2021, 12:12:38 am ---Question of course is: why would you implement basic logic gates and flip-flops in HDL? Other than as an exercise? (Which I suppose it is...)

Except for very particular cases, implementing such low-level logic in HDL is a pretty inefficient way of using a HDL. Just saying.

--- End quote ---

not only inefficient, that kind of async logic is also a bad match for an FPGA

You can build something from logic ICs and there are many of them that you can use.

FPGA is built the same way, it has blocks and interconnect. You connect the blocks pretty much the same way as you would connect logic ICs, except blocks are different - you won't fond JK flip-flops in FPGA, but you will find LUTs for example. There's some overlap - for example, D flip flops are present both in FPGA and logic IC series.

If you use logic ICs, it will never occur to you to build a LUT because you can use various ready-made gates instead.

Similarly, if you use FPGA, there's no point in building JK flip flops, because it's better to use resources which are already present in FPGA.

FPGA is actually much easier than logic ICs - the variety of blocks is not anywhere close to the variety of logic ICs and the blocks are more configurable. Not to mention the tools will build circuits for you.


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