I speak VHDL, not Verilog, so I'm afraid I can't help with your example - but...
All too often I see people trying to learn a hardware description language by coding individual logic functions, then trying to build those up into a model of the circuit they actually want - like you'd have to do if you were restricted to building your circuit using off-the-shelf components.
I've seen examples that show ridiculously simple logic - like, say, a single OR gate - and wrap it up in a process or even a whole component, then instantiate it at a higher level in order to actually use it. This is kind of OK as a way to demonstrate the syntax of the language, but as a way to learn how to really use HDL, it's terribly misleading.
The beauty of an FPGA is that you can describe the behaviour you want without having to worry about how that behaviour might, possibly, be realised using off-the-shelf logic gates. If you're following a tutorial or worked example which does spend more than a trivial amount of time creating complex circuits this way, I'd advise you to look elsewhere. Don't ever get into the mind set of building real circuits directly from these traditional building blocks; that's the job of the synthesis tool, not you.