Help with Altera Cyclone III configuration problems.

[Boscoe]

Hi,

I've tried to make a development board for the Cyclone III, most of it works as far as I can tell without the FPGA.

My problem is with the FPGA configuring after I have successfully downloaded the configuration file to the serial memory. Referencing this document:

https://www.altera.com/en_US/pdfs/literature/hb/cfg/cfg_cf51001.pdf

I can tell what stage the FPGA is in when powering up. Well nothing happens. The FPGA just sits there with NCONFIG at 1.5V, CONFIG_DONE at 0V and NSTATUS at 0V.

I think there may be something wrong with the FPGA as NCONFIG isn't at 0V, when I pull it low to reset the device and attempt to restart the configuration it drops a little to 1.2V.

I have gone over the pins and connection scheme and unfortunately haven't found any problems!

Attached is my schematic, it has some errors but I have made a rev1.1 schematic and changed those. One of those is the schematic says I'm using 1MB of memory when I'm using 16MB. I show rev1.0 as this is the revision of the board I'm working on.

Thanks for any help!

[Scrts]

NCE is pulled low by 10k. I think it has internal 10k pull-up. Pull that hard to GND with 0Ohm.

[Boscoe]

Thanks for your reply. It is pulled low in the schematic however I replaced the 10k with 0R and no change.

I decided to test whether the pad on the bottom had continuity to GND and it didn't so I fixed that and the FPGA configures from the memory however now Quartus Programmer does not recognise the memory when the pad is connected to GND. It works when I lift it.

[Scrts]

Can you program the FPGA using JTAG? Does CONF_DONE go up then?

[Boscoe]

Unfortunately I didn't bring the JTAG out and I can't mod it.

Do you have any other ideas?

I haven't had time to look at it since I got it working a bit. I have time tonight and see if I can solve it.

[deephaven]

Have you got MSEL 1, 2 and 3 set appropriately? See https://www.altera.com/en_US/pdfs/literature/hb/cyc3/cyc3_ciii51016.pdf

I have MSEL 2, 0 connected to 0v and MSEL 1 connected to Vdd.

[Boscoe]

Have you got MSEL 1, 2 and 3 set appropriately? See https://www.altera.com/en_US/pdfs/literature/hb/cyc3/cyc3_ciii51016.pdf

I have MSEL 2, 0 connected to 0v and MSEL 1 connected to Vdd.


Yes, that's how I've got them.

My problem is with nCE. When lifted Quartus downloads the data to the config device fine but the FPGA doesn't configure. If I then ground nCE, it configures and works but I can't download anything.

[Boscoe]

Okay I've got everything working now. It was because I shorted nCE to ground but in the app note it says to pull it to GND via 10k.