Hi,
I'm using Gowin FPGA, the part number is GW2AR-LV18QN88C8 which has 20K LUT and internal 64Mb SDRAM, I have designed a data logger, that would capture ADC data and saves it into internal SDRAM, the program should work as follow, it should save data a configurable amount of time for Pre and post trigger event, so I can see what was happening before and after the event,
I have applied a sine wave to the ADC, and the ADC core is working perfectly, it spit out ADC data to the Recorder logic, I think I have some problems with the Reading logic, I got some distortion in the read data logic, here is my Recorder state machine logic code,
I have tried many times to figure out what could be the problem?
Do you have any Idea what I might have done wrong?
Finally I have solved it!