Electronics > FPGA

How can I kill this bug in my Data logger Code?

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ali_asadzadeh:
Hi,
I'm using Gowin FPGA, the part number is GW2AR-LV18QN88C8 which has 20K LUT and internal 64Mb SDRAM, I have designed a data logger, that would capture ADC data and saves it into internal SDRAM, the program should work as follow, it should save data a configurable amount of time for Pre and post trigger event, so I can see what was happening before and after the event,

I have applied a sine wave to the ADC, and the ADC core is working perfectly, it spit out ADC data to the Recorder logic, I think I have some problems with the Reading logic, I got some distortion in the read data logic, here is my Recorder state machine logic code,





I have tried many times to figure out what could be the problem?
Do you have any Idea what I might have done wrong?

Finally I have solved it!

mfro:

--- Quote from: ali_asadzadeh on January 18, 2022, 09:09:01 am ---I have tried many times to figure out what could be the problem?
Do you have any Idea what I might have done wrong?

--- End quote ---

I do.

You missed to simulate your design. If you did, you would most likely already have found the problem.

Bassman59:

--- Quote from: mfro on January 18, 2022, 11:36:29 am ---
--- Quote from: ali_asadzadeh on January 18, 2022, 09:09:01 am ---I have tried many times to figure out what could be the problem?
Do you have any Idea what I might have done wrong?

--- End quote ---

I do.

You missed to simulate your design. If you did, you would most likely already have found the problem.

--- End quote ---

This is the way.

SiliconWizard:
Ditto. I can't even understand the idea of trying to debug a design written in some HDL without simulation. At best, this is usually terribly inefficient, and at worst, you may just never figure it out and claim that FPGAs are crap. (A less generalized variation of this would be to put the blame on the FPGA vendor. Yes, I've seen this. ;D )

ali_asadzadeh:
I know the way to do it is simulation :)
The problem is that I'm using Gowin Internal SDRAM IP and unfortunately Gowin does not provide any means for simulation their IP.
So Imagine that you have a Black box in your FPGA design that you can not simulate it, how do you solve your problems?

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