Author Topic: How do I write VHDL that can keep up with a 6.6Gb/s GTP?  (Read 999 times)

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Offline dnhkngTopic starter

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How do I write VHDL that can keep up with a 6.6Gb/s GTP?
« on: July 01, 2020, 06:19:03 pm »
I'm pretty new to FPGA, but one thing I don't get is how the FPGA can keep up with high-speed serial.

I had some designs I couldn't get to even 150MHz,  and if the deserializer is reading bytes for a 6.6Gb/s stream, that's not fast enough to process the incoming information.

Am I missing something?
 

Offline filssavi

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Re: How do I write VHDL that can keep up with a 6.6Gb/s GTP?
« Reply #1 on: July 01, 2020, 06:27:29 pm »
I never used the GTPs, however I guess you want to use hard SERDES blocks to do convert the stream to as wide as possible, 10/30 bytes I guess, and then do stuff in parallel, otherwise it is just like drinking from a firehose

If the transmissions are bursty You might also get away with pushing everything to a Ram block and then do processing  slowly
 

Online AndyC_772

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Re: How do I write VHDL that can keep up with a 6.6Gb/s GTP?
« Reply #2 on: July 01, 2020, 06:32:56 pm »
Hard wired SERDES blocks. The FPGA is mostly configurable logic, which is versatile but relatively slow, but also includes optimised, hard wired circuits for common logic functions such as multiplying numbers, dual port RAM, and in this case, parallel-to-serial conversion.

As far as your logic is concerned, a 6 GHz "serial" interface could actually look like a 32 bit parallel interface clocked at around 200 MHz, which within the confines of the FPGA die, is more manageable.

Offline Bassman59

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Re: How do I write VHDL that can keep up with a 6.6Gb/s GTP?
« Reply #3 on: July 01, 2020, 06:55:36 pm »
I'm pretty new to FPGA, but one thing I don't get is how the FPGA can keep up with high-speed serial.

I had some designs I couldn't get to even 150MHz,  and if the deserializer is reading bytes for a 6.6Gb/s stream, that's not fast enough to process the incoming information.

Am I missing something?

The deserializer is a hard block in the FPGA, and you access it in your code by instantiating a library element.

The output of the deserializer is parallel data words of some given length that is dependent on how the deserializer is configured. That parallel bus runs at a fraction of the rate of the gigabit data stream, and should be manageable in your larger FPGA design.

Also, I don't think they'd put such a high-speed deserializer in the FPGA if the fabric itself couldn't handle the deserialized data.
 

Offline dnhkngTopic starter

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Re: How do I write VHDL that can keep up with a 6.6Gb/s GTP?
« Reply #4 on: July 01, 2020, 07:48:51 pm »
Thanks, I think it makes sense now!
 


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