Hard wired SERDES blocks. The FPGA is mostly configurable logic, which is versatile but relatively slow, but also includes optimised, hard wired circuits for common logic functions such as multiplying numbers, dual port RAM, and in this case, parallel-to-serial conversion.
As far as your logic is concerned, a 6 GHz "serial" interface could actually look like a 32 bit parallel interface clocked at around 200 MHz, which within the confines of the FPGA die, is more manageable.