How exactly does differential signal lead to low power consumption in FPGAs?

[matrixofdynamism]

Differential signals use two lines instead of one. This means twice the switching activity compared with use of single ended transmission. How then does use of differential signalling achieve lower power in FPGAs since power dissipation mainly occurs when output is switching state?

[ataradov]

What makes you think differential signalling leads to low power consumption?

Its primary use is for noise immunity. Generally differential voltage may be lower than single-ended, but at high data rates typically associated with the differential signalling, I doubt there is a lot of room for power saving.

[pigrew]

One reason is that differential signaling usually has much lower voltage swings. LVDS swings only about 0.4 V on each track (versus perhaps 1.8 V for a single-ended signal).  LVDS has a constant 3.5 mA output (at all times), so it burns about 12 mW (its power consumption does not increase much with signaling rate).

Differential signaling allows lower signal voltages (hence, lower power), with superior noise immunity.

At low frequencies, LVDS would have a higher power consumption than single-ended. But, there would be some frequency at which LVDS becomes lower power.

(Single-ended power is mostly due to load capacitance charging, f*C*Vdd^2.)

(The LVDS power of Vdd*3.5mA is a bit simplistic. Other parts of the driver will use power, and the output current could even vary over time due to things like equalization.)

[matrixofdynamism]

Differential signalling will probably need some sort of termination. If this is ground termination, it means that there will always be current sinking into ground when the buffer is driving a logic high. Does this not mean that differential signalling will lead to higher power dissipation than single ended?

[asmi]

Differential signalling will probably need some sort of termination. If this is ground termination, it means that there will always be current sinking into ground when the buffer is driving a logic high. Does this not mean that differential signalling will lead to higher power dissipation than single ended?

Most differential standards use differential termination (when resistor is between positive and negative lines), Though there are other standards - notably, HDMI used single-ended termination to the Vcc.

[asmi]

How then does use of differential signalling achieve lower power in FPGAs since power dissipation mainly occurs when output is switching state?

As was said above, low power is achieved by using very low voltage swing. Incidentally, this is how standards like DDR3L lower power consumption as well - even though they are single-ended, they deviate from the reference value (which is midpoint, Vcc/2, 0.675 V) by only 90 mV in some cases. This not only reduces dynamic power consumption (switching loss), but also drastically reduces losses of power on termination (as DDR3L signals are terminated to the reference midpoint voltage).

[matrixofdynamism]

What do you mean by "deviate from reference value"? Single ended signals are referenced to ground are they not?

[ataradov]

No, single-ended signals may have any reference value you like. In that case your "0" would be (675-90) mV and "1" (675+90) mV. With some margins, of course. Overall both those values are measured from the common ground, of course.

The logic level is recovered using fast comparators in this case. And they are fast because they never go into saturation because of the way reference level and deviation were chosen.

[David Hess]

The difference is noise immunity between differential and single ended signals is responsible for the difference in power consumption.  The differential signal rejects common mode noise at the receiver so a smaller signal level is acceptable.  For instance GTL (Gunning Transistor Logic) uses 40 milliamps to produce a voltage swing of 1 volt into 25 ohms while LVDS (Low Voltage Differential Signalling) uses 1/10th of that current to produce twice the voltage into 50 ohms or 0.2 volts.  The difference in impedance helps and comes about because with differential signalling, two transmission lines are used effectively in series.  Note that the same LVDS driver drives two series connected transmission lines so the impedance is doubled and the same current source/sink is used for both.

[asmi]

No, single-ended signals may have any reference value you like. In that case your "0" would be (675-90) mV and "1" (675+90) mV. With some margins, of course. Overall both those values are measured from the common ground, of course.

The logic level is recovered using fast comparators in this case. And they are fast because they never go into saturation because of the way reference level and deviation were chosen.

Yea, the obvious downside is it doesn't take all that much to flip the bit via crosstalk. Which is why DDRx layouts become so finicky as the frequency goes up.

[David Hess]

Yea, the obvious downside is it doesn't take all that much to flip the bit via crosstalk. Which is why DDRx layouts become so finicky as the frequency goes up.

Often as with current DRAM standards, the reference for the logic threshold is available externally which improves the situation somewhat.  ECL is based on differential inputs but one is tied to a reference and in some cases, this was made available externally, so it is an old idea.

The more critical DRAM signals are provided differentially.

One trick parallel single ended buses use now to lower power is an "invert" signal which inverts the logical meaning of the logic levels on the bus.  So if there are more 0s than 1s which would draw more power from high side terminations, the logical meaning can be reversed to swap the higher current 0s for lower current 1s.

[T3sl4co1l]

Consider a few facts:

1. Signalling rates that are high enough that the delay time of the trace (let alone anything going over cables) is substantial, i.e. > 1/10th bit time.
2. This necessitates termination to address ISI.
3. A CMOS pin driver (transmitter) pulls to the rails, whatever that may be, 1.8V, 2.5V, 3.3V.
4. The CMOS driver is usually source terminated (whether by setting Rds(on) in the ballpark, or adding explicit internal or external termination resistance), so we can avoid DC losses at the load, and can use full-swing inputs (CMOS receivers, just plain old inverters with 30%-70% input voltage threshold, plus the usual ESD protection).

Putting all these facts together, we observe supply current goes up proportionally with signal rate, until as we approach the delay > 1/2 bit time range, it levels off at around Vdd^2 / (4 Zo).  That is, the mean transmission line voltage is Vdd/2, so we drive pulses of Vdd or Vss into it, dropping (Vdd/2) across the termination resistance.

This is in addition to internal gate losses (equivalent switching capacitance), which isn't at all negligible for CMOS at these voltages and rates, it still goes up proportionally.

The simple fact is we're driving whole volts into a ~100 ohm transmission line and termination, and doing this at Gbps is intensive.

And furthermore, not to mention the demands placed on supply and grounding: such a transmitter would need multiple pins adjacent, and even then might not be adequately bypassed, in a packaged device (i.e., due to the leads or bondwires in a QFP or QFN).

So we would like to solve multiple problems at once.

- We can solve the supply and grounding problem, by using steered constant currents.  Old school ECL* does this internally (the input stage is a differential pair), and externally if used appropriately (the outputs are always(?) complementary).  LVDS does this explicitly, where the transmitter is a current-sourced H-bridge.  (It's not using perfect switches, which actually helps as the softness defines a modest common mode impedance for the pair, setting CM bias, and termination to some extent, at the same time.)

*Which hasn't gone away at all, ECL is still very much around; I guess it should be called just "school".   I don't run across it much in common modern digital interfaces, but it's still plenty popular for lower level stuff, precision timing, etc.

- We can solve the equivalent capacitance problem, by using ever-smaller fabrication nodes, and lower supply voltages.  Hence the typically 0.9-1.2V core voltage on anything reasonably complex.  We still need level shifters out to the IO pads, but we don't have to do all the logic at the IO voltage.

- And we can solve the signal level problem, by simply using less signal.  This necessitates a different input stage, usually a complementary differential pair, much like any other rail-to-rail comparator (and indeed, LVDS receivers can often be (ab)used in this way).  The input stage is much more complex, but that's alright.  Once it's solved, it's solved (i.e., fabs having standard library solutions or whatever).

That leaves the DC consumption problem, which is unfortunate, but there are solutions for that as well.  MIPI for example, only asserts the bus when data is being transmitted, saving nicely for mobile devices with intermittent display updates.  Think, scaled down and greatly sped-up RS-485.

Or, I don't know if PCIe does a similar thing or what exactly, but it's also AC coupled so it physically cannot deliver DC; receivers then need their own DC bias (and probably ALC or DC-restore or something like that), and also it has even more complexity (clock recovery for starters).  But yeah, again, in the Gbps it's going to be complex and that's why we have 10s-nm core logic to handle all that stuff.


Whereas, down in the Mbps, you wouldn't bother with any of this stuff, it's not anywhere near worth the complexity -- and the loss due to charging relatively very short transmission lines to modest supply voltages, isn't a big expense, so that's why we stick with plain old CMOS there.

Tim

[David Hess]

Whereas, down in the Mbps, you wouldn't bother with any of this stuff, it's not anywhere near worth the complexity -- and the loss due to charging relatively very short transmission lines to modest supply voltages, isn't a big expense, so that's why we stick with plain old CMOS there.

Speak for yourself.  I have designed and implemented discrete bipolar current mode RS-232 level shifters and they performed gloriously.   

[T3sl4co1l]

Or if you're really old, I²L.

Tim

[David Hess]

I still want to make a digital clock using discrete transistors for I²L.  Would that make it DIL (Discrete Injection Logic)?  That would be too bad as I hate dill.

[T3sl4co1l]

That one TI LED watch chip has been reversed, hasn't it?

Tim

[David Hess]

That one TI LED watch chip has been reversed, hasn't it?

It is mentioned here but I do not remember it being reverse engineered:

http://www.righto.com/2020/09/inside-hp-nanoprocessor-high-speed.html

I would not need details of the Texas Instruments chip; the logic design is straightforward and I have done it before.  The fun would be implementing functions without logic gates to save complexity from a gate only design.  Unfortunately discrete injection logic cannot take advantage of the virtues of integrated injection logic.

[matrixofdynamism]

Lets take example of Texas Instruments ADS4126. The datasheet has "ELECTRICAL CHARACTERISTICS: GENERAL" on page 7. It shows the Analog Power when LVDS interface and CMOS interface are used. The CMOS interface shows lower power dissipation. Does this mean that he power dissipation at 120M SPS data rate is actually lower for CMOS rather than the LVDS?

[ataradov]

LVDS in this case is carried over the same set of pins, and uses DDR signalling. So the frequency on the data pins is two times higher.