How in the world do i get started

[OverlordCheese]

I'm gonna make this real simple because Ive been spending the past 4 hours working on this one part and I dont know what to do
and its really not that complicated:
Ideally, it would be amazing if I could create a logic diagram and the program would create code from that diagram, or something similar.
I need it on linux, and I need to actually be able to install it.
Please, I am fucking desparate.

[ataradov]

There is no such thing. Especially nothing that is easier to use than just writing Verilog code directly. If you have a logic diagram, translating it do the code is generally not that hard.

If the diagram is not secret, share it and your attempts. You may be missing something simple.

But also, is 4 hours your entire experience with FPGAs and HDLs? This is clearly not enough to learn anything.

[rstofer]

Xilinx ISE had Schematic Entry but it didn't create 'code'.  It just laid down logic along with the rest of the project.  I don't know if it worked on Linux.

As ataradov said above, post your schematic and maybe someone will take a crack at it.

Here's a pretty good book for VHDL:
https://www.isy.liu.se/edu/kurs/TSEA83/kursmaterial/vhdl/free_range_vhdl_2019.pdf

Here's another resource:
https://nandland.com/

[ataradov]

ISE did work on Linux, but even when it did, schematic entry was obsoleted. Now ISE itself is obsoleted. That is the definition of "not worth it".

[rstofer]

ISE did work on Linux, but even when it did, schematic entry was obsoleted. Now ISE itself is obsoleted. That is the definition of "not worth it".

I used it about 15 years ago to create a full adder that I couldn't seem to code (noob).  It worked fine but, as you said, ISE is obsolete and I moved on.  It was more work than it was worth.

[Someone]

Altium did (does?) have schematic to HDL generation
Linux? nope
Free? nope

What's your time worth? What's my time worth?

As above, just learn direct to HDL. The many downsides with schematic entry have made it an obsolete/legacy method of logic design.

[james_s]

I still use ISE and Quartus, they work as well today as they ever did, and both do have schematic entry. IMHO it is a waste of time though because VHDL or Verilog are SO much easier to maintain once you get them.

You need to spend a lot more than 4 hours though, I probably spent 100 hours before I could write basic VHDL code that would compile into something useful. There's a free ebook called Free Range VHDL which I found very helpful.

[Mario87]

There is no such thing. Especially nothing that is easier to use than just writing Verilog code directly. If you have a logic diagram, translating it do the code is generally not that hard.

While I agree that verilog is probably the easier / quicker option if you know it, for the OP, they could create a block design in Vivado with a load of logic gates, then they only need to create a basic top module to instantiate the physical outside world connections to the inputs and outputs of their logic block design.

Don't think Vivado works on Linux though.

Also, as mentioned already, 4 hours really is not much time at all, took me around 3-6 months to become proficient with Verilog and FPGA's in general.

[woofy]

I've tried schematic input with ISE, but its an absolute nightmare. The slightest change requires massive re-editing of the schematic. In the end the same thing could be done with just a few lines of HDL.
Forget schematic input and go with Verilog or VHDL I prefer Verilog. A great learning resource is https://nandland.com/

[Sal Ammoniac]

I would second the Free Range VHDL suggestion. I went from knowing nothing about FPGAs to being able to write VHDL that implemented simple constructs like clock dividers and simple state machines in just a few days. Another advantage is that it's free. Download it from here: https://www.isy.liu.se/edu/kurs/TSEA83/kursmaterial/vhdl/free_range_vhdl_2019.pdf

[rstofer]

Then there's the MATLAB HDL Coder - I haven't used it but it seems to want to take Simulink designs or MATLAB functions and implement them in hardware.  Simulink designs are graphical and I suppose you could use logic devices in the design.

https://www.mathworks.com/products/hdl-coder.html#featured-applications

Mathworks has a lot of documentation including how to create a D flop.

[PatrickCPE]

Vivado does work on Linux. I've tested on both Ubuntu 18 and Ubuntu 20, but I do think the support for 20 was rather recent. They have a list of supported distros but I believe it's either Ubuntu, RHEL, or Suse Enterprise.

I read on their forums installing on Debian is just a matter of changing a one liner in a bash script.

And for the person who started the thread everyone is going to say do Verilog or do VHDL. I recommend you just look on something like Indeed and see what companies near you use. Pick the one they do. In terms of getting started I'll give you the free online sources I know of. I'd also see if they ask for experience with Intel/Alterra or Xilinx/AMD. If they want Alterra install Quartus and use that toolchain, and if they want Xilinx install Vivado. Optionally start with the Lattice tools because they're cheap

1. Nandland (https://nandland.com/) - Excellent source for beginner and intermediate tutorials in both written and video format. He has a Lattice dev board that he talks you through using as well, highly recommend starting here.
2. Asic World (https://www.asic-world.com/) - Awesome reference for all things HDL. He does a lot of stuff for Design verification alongside tutorials for Verilog, System Verilog, VHDL, and others. I can only vouch for Verilog and System Verilog but it's a great reference
3. ZipCPU (https://zipcpu.com/) - His beginner tutorial I'd argue is much more than a beginner guide, but an excellent series none the less. He teaches you how to write Verilog, do C++ simulation via a simulator called Verilator, and how to do formal proofs. One of the highest quality series out there, but Verilator is a tool that is more niche than just writing your testbench in the HDL you'll be using (Verilog or VHDL). If you find you like this stuff I recommend you check him out

[james_s]

And for the person who started the thread everyone is going to say do Verilog or do VHDL. I recommend you just look on something like Indeed and see what companies near you use. Pick the one they do. In terms of getting started I'll give you the free online sources I know of. I'd also see if they ask for experience with Intel/Alterra or Xilinx/AMD. If they want Alterra install Quartus and use that toolchain, and if they want Xilinx install Vivado. Optionally start with the Lattice tools because they're cheap

That depends on whether they hope to do it as a career, which is difficult, there are not a lot of FPGA jobs out there and those that exist usually demand a high level of proficiency. For myself I was really only interested in FPGA development as a hobby and there seemed to be a LOT more VHDL out there than Verilog. Which language to use can be a bit of a religious argument but in the end they both have exactly the same capability and anything that can be modeled in one can be modeled in the other. Personally I found VHDL to make a lot more sense to my brain and it was a lot easier to find good tutorials. Verilog looks like abbreviated gibberish to me but many people love it. I'd suggest trying both and stick to whichever one works best for you. You can even mix & match multiple languages in the same project fairly easily.

[Sal Ammoniac]

If you're going to do FPGA development professionally, you need to know both SystemVerilog and VHDL. Even if you only write in one, you will need to read and understand the other because a lot of IP will be available in the other language.

[Scrts]

I'm gonna make this real simple because Ive been spending the past 4 hours working on this one part and I dont know what to do
and its really not that complicated:
Ideally, it would be amazing if I could create a logic diagram and the program would create code from that diagram, or something similar.
I need it on linux, and I need to actually be able to install it.
Please, I am fucking desparate.

Is this for FPGA logic? Like Aldec Active HDL Design Entry https://www.aldec.com/en/solutions/fpga_design/graphical_text_design_entry
Or this is for SCADA?
Or this is high-level code generation, like MatLab Simulink?

[mon2]

@Sal, Gazoo ??

Yabba, Dabba, Do
Yabba, Dabba, Do
Take me to your leader!

To the OP, review this website - Jean is amazing on the wealth of information on getting started - we are not pros by any means but have learned a great deal on using verilog. Far too many toolchains have been broken by the factory (Lattice, Gowin, Efinix - each has had issues - Lattice still has buggy docs on their website and are in denial. Some tech support cases were raised WITH our corrections, yet years later, still not corrected. Same with Silabs and their dreaded C2 specification - stuck @ v1.4 docs. The Cygnal original version was correct but broken by Silabs).

https://www.fpga4fun.com/

Pickup the Gowin myminieye kit from Amazon or Aliexpress to start your learning. Can help with that if you proceed.

https://magicjellybeanfpga.github.io/mjb/

We have this one:

https://www.amazon.com/Gowin-MiniStar-Experiment-Kit/dp/B09C64617X?ref_=ast_sto_dp