How modeling static RAM in Verilog

[BrianHG]

(Also, next time you try a project like this, maybe use multiple sub schematic pages like your source TTL schematic, and have a 'top' hierarchy schematic wiring those sup pages together and also wire to the selected FPGA IO pins.)

Yes, I tried to split the whole schematics into sub pages but, after researching, it seems it's not possible under Quartus.

LOL, did you even try any of the tutorials?
Did you even try to Youtube search Quartus schematic entry tutorials?
I've been using Quartus since the early 2000's and I have may multipage schematics.

Did you not think to make a schematic with input, output and bidir pins?
Then, 'generate a block symbol' for that schematic sheet?
Then you could place any 1 or multiple of those generated block symbols on any other schematics...

See my attached project, no problems here...

[caius]

LOL, did you even try any of the tutorials?
Did you even try to Youtube search Quartus schematic entry tutorials?
I've been using Quartus since the early 2000's and I have may multipage schematics.

Yes, sorry, I have  to study more 

Did you not think to make a schematic with input, output and bidir pins?
Then, 'generate a block symbol' for that schematic sheet?
Then you could place any 1 or multiple of those generated block symbols on any other schematics...

Do you mean a Quartus block schematics with input, output and bidir pins thren assigned to I/O of the FPGA?I put I/O on top of my messy block schematics if you mean this 

See my attached project, no problems here...

Many thanks.I can see you did a single 512x8-bit RAM module instead of two 256x8-bit ones.Now I have to figure out how to interface it to my messy schematics (first of all I have to change label names, I think)
Shame that the Verilog code (not made by me) is mostly working, just few glitches.But, as you guys said, perhaps it can't run on a FPGA.

[BrianHG]

Many thanks.I can see you did a single 512x8-bit RAM module instead of two 256x8-bit ones.Now I have to figure out how to interface it to my messy schematics (first of all I have to change label names, I think)
Shame that the Verilog code (not made by me) is mostly working, just few glitches.But, as you guys said, perhaps it can't run on a FPGA.

It can run on a FPGA, you just need to be a little more smart about it.

Take a look at my Quartus project I sent you.  Notice the schematic with the onship memory.  It shows you that there is a DFF latch for the input controls on that memory.  This means in your schematic, the BARRY DEVIN and DONNY are already located inside the startic ram's block diagram, (I hope you double clicked on it to see the inside...) this means to match your schematic functions, you need to omit those 3 ICs and just feed their clock into the block-ram's clock.

Most of everything else should just match away...

Another thing, get rid of the way my tristate is wired.  Remove LOIC and LEO, they are only a buffers feeding in the static ram's DATA-INPUT port.  Just wire the bidir pins PIN_D[0..7] to the onchip memory DIN while the memory output is wired through a tristate to the bidir pins for output.

Glitches means timing constraints errors.  Did you create a .sdc constraints file?

Do you mean a Quartus block schematics with input, output and bidir pins thren assigned to I/O of the FPGA?I put I/O on top of my messy block schematics if you mean this 

The input, output and bidir pins only go to pin if they are on the top hierarchy schematic sheet.  On all other sub-schematic sheets, those pins become input and output ports for the symbol you generate which you can place on any other higher level schematic sheet.

[caius]

It can run on a FPGA, you just need to be a little more smart about it.

It would be great

Take a look at my Quartus project I sent you.  Notice the schematic with the onship memory.  It shows you that there is a DFF latch for the input controls on that memory.  This means in your schematic, the BARRY DEVIN and DONNY are already located inside the startic ram's block diagram, (I hope you double clicked on it to see the inside...) this means to match your schematic functions, you need to omit those 3 ICs and just feed their clock into the block-ram's clock.
Most of everything else should just match away...

Yes, I did see, many thanks.I guess the 'caius_top.bdf' is the top of hierarchy and this is what I have to insert in my schematics.What is unclear to me is which labels I have to change in this block to be adapted to my schematics.

Another thing, get rid of the way my tristate is wired.  Remove LOIC and LEO, they are only a buffers feeding in the static ram's DATA-INPUT port.  Just wire the bidir pins PIN_D[0..7] to the onchip memory DIN while the memory output is wired through a tristate to the bidir pins for output.

Yes, I can see.This means I have to remove all the BUF_D[7..0] labels in the whole schematics and use the PIN_D[7..0] instead (see the two 74283 JASON-GRACIE, the two 74157 JASON2-JOSHUA and the two 74373 KARSON/LUKE and JACK/JOHN)

Glitches means timing constraints errors.Did you create a .sdc constraints file?

No, I have not created a .sdc constraints file, I always thought it was not really important.Anyway, the glitches are when  I try the Verilog file, the block schematics are still untested on MAX10 FPGA until I get them succesfully compiled in Quartus.I posted the Verilog code above, almost perfect on MAX10, maybe we can work on it and improve it instead of doing Quartus block schematics?I don't know and ask you,  expert guys, which is the best solution.

 

The input, output and bidir pins only go to pin if they are on the top hierarchy schematic sheet.  On all other sub-schematic sheets, those pins become input and output ports for the symbol you generate which you can place on any other higher level schematic sheet.

Got it.I usally use inputs, output and bidir pins to FPGA I/O on the whole schematics and  then use wires with labels to the inputs and outputs ports of the symbols  (more or less like I do in KiCad with global lables)

P.S.
I attach the Quartus project folder, it's better than an exported .jpg.

[BrianHG]

If you problem is glitches, not full functionality, have you tried inverting the incoming clock?

Does you incoming clock go through a 'GLOBAL' dedicated clock input and go through a 'GLOBAL CLK' buffer?

Did you try put the input clock through a PLL set to 1:1 and adjust the output clock phase, or use multiple PLL output clock phases like 0deg, 90deg, 180deg, 270deg, and use those output for separate sections of your design?

Remember, internally, the FPGA will do some thing much faster than TTL ICs.  Using delayed clocks in the right places may help.

Also, are you using the SignalTap/2 to realtime see what's happening inside your FPGA as it runs.

[caius]

If your problem is glitches, not full functionality, have you tried inverting the incoming clock?

Yes, I tried to invert the clock with no success

Does you incoming clock go through a 'GLOBAL' dedicated clock input and go through a 'GLOBAL CLK' buffer?

It goes to pin 27 of the MAX10 FPGA (whch shod be a dedicated CLOCK input) directly and not through a 'GLOBAL CLK' buffer.

Did you try put the input clock through a PLL set to 1:1 and adjust the output clock phase, or use multiple PLL output clock phases like 0deg, 90deg, 180deg, 270deg, and use those output for separate sections of your design?

I used a PLL (8MHz:8MHz) like you suggested me in the other thread , this improved things close to perfection , now left only some garbage objects (not really "glitches")  on a specific game board (all the other run fine wit the FPGA replacement)

Remember, internally, the FPGA will do some thing much faster than TTL ICs.  Using delayed clocks in the right places may help.

Yes, I know FPGA is much faster than TTL ICs, this is where the problem lies IMHO but I'm not able to pinpoint and debug it.That's why I decided (instead of using the Verilog code made by the author of schematis) to translate the TTL schematics into Quartus block schematics to see if, at least, that garbage goes away.But, until I'm not able to compile and synthetize the Quartus block schematics I can't try anything.

Also, are you using the SignalTap/2 to realtime see what's happening inside your FPGA as it runs.

No, I'm not using it.Also, I have no scope at the moment, only a cheap logic analyzer.I may hook up this on outputs of the FPGA and compare them to the outputs of original custom IC.

[BrianHG]

Also, are you using the SignalTap/2 to realtime see what's happening inside your FPGA as it runs.

No, I'm not using it.Also, I have no scope at the moment, only a cheap logic analyzer.I may hook up this on outputs of the FPGA and compare them to the outputs of original custom IC.

Signal tap gives you a digital logic analyzer of the FPGA IOs and internals.
Instead of a scope, get a USB based 16 channel logic analyzer for your PC.
EG: (now, I'm not condoning this brand, but if 8 channel 24mhz is enough for your 8mhz Z80, maybe or something a bit better)
Dirt junk logic analyzer
Much more respectable

Don't forget to try different clock phases for the IO buffers and the internal ram.
Also try to clock the ram at 2X speed, 16Mhz.  This will make it appear more like static ram.

If the PLL helped lower the glitching, the finalizing the .sdc file, or even the basic simplest .sdc entry for the PLL alone may help clean up the remaining junk.


Also, for slow IOs, you can set the input/output pin speeds to slow slew rate or play with the drive current for the output pins.

[caius]

Signal tap gives you a digital logic analyzer of the FPGA IOs and internals.
Instead of a scope, get a USB based 16 channel logic analyzer for your PC.
EG: (now, I'm not condoning this brand, but if 8 channel 24mhz is enough for your 8mhz Z80, maybe or something a bit better)
Dirt junk logic analyzer
Much more respectable

I have this logic analyzer :

https://hobbycomponents.com/our-brand-exclusives/1000-hobby-components-16-channel-logic-analyser

Don't forget to try different clock phases for the IO buffers and the internal ram.
Also try to clock the ram at 2X speed, 16Mhz.  This will make it appear more like static ram.

How to try the clock phases on IO buffers and internal RAM or clock the RAMs at 16MHz?I'm now using the Verilog file and not Quartus schematics where I could see and wire the RAMs blocks.
@BrianHG, I was not able to implement your 'caius' project you kindly earlier posted on this thread.Maybe you can look at it?I posted the whole Quartus schemarics prjoject earlier.Just to clear, I don't want ready-made food from you because I want to learn myself!  (sadly, time for me is a big issue since I live alone and must do all by myself, my life is very hectic  )

If the PLL helped lower the glitching, the finalizing the .sdc file, or even the basic simplest .sdc entry for the PLL alone may help clean up the remaining junk.

Yes, I already set the PLL you kindly gave me in the other thread here and had big improvements :

https://www.eevblog.com/forum/fpga/help-on-translate-schematics-to-verilog/msg5483155/#msg5483155

I wanted to create an .SDC file but it seems Quartus Prime 17 (the version I'm using) has no wizard for the the TimeQuest Timing Analyzer (unlike version 13 which has it).May I create the .SDC file with TLC syntax?Anyway, there some values (tsu, th, etc..) I must figure out

Also, for slow IOs, you can set the input/output pin speeds to slow slew rate or play with the drive current for the output pins.

Already tried the SLOW SLEW RATE and different settings of drive current on the PIN Planner with no improvements or changes.

[BrianHG]

@BrianHG, I was not able to implement your 'caius' project you kindly earlier posted on this thread.Maybe you can look at it?I posted the whole Quartus schemarics prjoject earlier.Just to clear, I don't want ready-made food from you because I want to learn myself!  (sadly, time for me is a big issue since I live alone and must do all by myself, my life is very hectic  )

Start a new blank project from scratch with a new name.
Make a block diagram with an input and 2 output pins.
Go into the megafunctions and look for clocking and select the normal PLL.
Configure your PLL clock for 1 input at 8mhz and 2 outputs at 8mhz and 16mhz.
Make sure the .bsf [ x ] is selected to be generated before you finish (block symbol file)

Now, double click on a blank section of your schematic and select in the available dropdown directories your project directory.  You will see your PLL there.  Place it on the sheet.
Tie the inputs and outputs.

Start analysis and elab int the compile menu.
Assign IO pins numbers to your ins and outs.
Do a full compile.

Verify that your PCB works.,

Next, add your address and data IO pins.
Go into the megafunctions section for onchip memory an create a 512x8 ram chip with the features you want.
Make sure the .bsf [ x ] is selected to be generated before you finish (generate a block symbol file)

Now, double click on a blank section of your schematic and select in the available dropdown directories your project directory.  You will see your PLL and new memory there.  Place it on the sheet.
Tie the inputs and outputs.

Compile.


If working, delete the ram.
Make a new schematicblock diagram called memory section.
Inside that document, place the memory there.
Remember, you can copy and paste objects from schematic sheet to another schematic sheet so long as all the custom components exist in you project library.


AGAIN, go to youtube and watch some Quartus tutorials by Altera or any third party Youtuber.  These things should be somewhere out there.

[caius]

Thanks BrianHG for putting your time on this.I will try ASAP but no success is guaranteed here 

P.S.
I see Quartus megafunction of RAM lacks of CHIP SELECT input, how to hande this since RAMs in my schematcs do have it ?

[BrianHG]

Thanks BrianHG for putting your time on this.I will try ASAP but no success is guaranteed here 

P.S.
I see Quartus megafunction of RAM lacks of CHIP SELECT input, how to hande this since RAMs in my schematcs do have it ?

Chip select should just go though a gate with the write enable to drive the write enable on the ram.
Also, in the ram megafunction setup page, you will see an option to enable an 'read and write enable' input ports.

Remember, those ports are positive logic.

[caius]

Chip select should just go though a gate with the write enable to drive the write enable on the ram.
Also, in the ram megafunction setup page, you will see an option to enable an 'read and write enable' input ports.

I followed your steps and miserably failed.I attach the "memory" project.When I implement it in my schematics  and try a compile I get the same errors about some pins configting (those BUF_D[7..0]) with mutiple drivers (log attached).
I attach also my Quartus schematics again if someone wants to take a look.
Here's how the garbage graphics is displayed on screen when I try the FPGA replacement running the attached Verilog code.You can see the junk generated on power up and then stay on screen, this lead me think some wrong data is written on RAM (due to timing issue, perhaps?)

https://youtu.be/KhEuuS7UCbI

Remember, those ports are positive logic.

Yes, I know they are active HIGH while in my schematics they are active LOW.I can I can use an inverter on each port of simulate RAM, I think