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How modeling static RAM in Verilog

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caius:
Hi all,
it came the time for me to model a static RAM in Verilog.I'm uncertain if using registers or block, the RAM must be static therefore asynchronous.I attach the schematics (one RAM must be 256X8, the other 128X8)
Thanks in advance for any help or advice.

P.S.

The models will run on MAX10 FPGA.

woofy:

--- Quote from: caius on October 31, 2024, 10:11:49 pm ---Hi all,
...  the RAM must be static therefore asynchronous. ...

--- End quote ---
static rams can be synchronous, and when inferring an fpga's built in ram blocks, usually are.

I've not used the max10, but the ice40 example below should be very similar.


--- Code: ---module DataRam (din, write_en, waddr, raddr, clk, dout);
parameter addr_width = 10;
parameter data_width = 8;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, clk;
output reg [data_width-1:0] dout;

reg [data_width-1:0] mem [(1<<addr_width)-1:0];

   initial begin
     $readmemh("dta_data", mem); // dta_data - the initialised 8-bit ram
   end

always @(posedge clk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end

always @(posedge clk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end

endmodule
--- End code ---

nctnico:
Generally speaking: if you infer asynchronous RAM, the synthesizer will be forced to use flipflops and/or LUTS. With synchronous RAM, the synthesizer can choose what is most efficient (synchronous block ram or use LUTs / flipflops anyway).

caius:
Thanks for answers.I found this module for a 2K X 8Bit RAM, maybe I can adapt it for my needs :


--- Code: ---module ram
#(
  parameter addr_width=12,
  parameter data_width=8
)
(
  input clk,
  input [addr_width-1:0] addr,
  input [data_width-1:0] din,
  output [data_width-1:0] q,
  input rd_n,
  input wr_n,
  input ce_n
);

reg [data_width-1:0] data;
reg [data_width-1:0] mem[(1<<addr_width)-1:0];

assign q = ~ce_n ? data : 0;

always @(posedge clk) begin

  if (~rd_n) data <= mem[addr];
  if (~wr_n & ~ce_n) mem[addr] <= din;

end


endmodule
--- End code ---

BrianHG:
You didn't set an optional attribute for your:

--- Code: ---reg [data_width-1:0] mem[(1<<addr_width)-1:0];
--- End code ---

Read here: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram.htm

or a default init file:
Read here: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram_init.htm

or default power-up initialization value like:

--- Code: ---reg [data_width-1:0] mem[(1<<addr_width)-1:0]  = '{default:'0} ;
--- End code ---

or in-line coded assigned init values like here:
https://github.com/BrianHGinc/BHG_I2C_init_RS232_debugger/blob/8a607f0d0aebf0e0bc151308c545c21822d9936b/hdl/BHG_I2C_init_RS232_debugger.sv#L495

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