Electronics > FPGA

How to add in Verilog? Quartus, EPM7064STC44 etc.

(1/1)

NivagSwerdna:
So following on from my other thread I am essentially going to try to target a EPM7064STC44 and develop in Verilog using Quartus II 13.x...

All is going well for my first design... so moving to my second...

I have 2 values (both 8-bit unsigned) that I have to add together and then add 1... I need to produce the output.

Now simplistically...

adj_value = value1+value2+1

This works but produces some interesting output...

Info (278001): Inferred 1 megafunctions from design logic
Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0"
Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0"

OK... well if it wants to I suppose it can...

but this one is a bit more worrying...

Warning (10230): Verilog HDL assignment warning at Thing.sv(25): truncated value with size 32 to match size of target (8)

I have...

reg [7:0] adjusted_value;

always @(posedge s1_i) begin
   adjusted_value = value1+value2+1;
end

So really I just want an 8 bit full adder (where I can use the lowest carry to incorporate my +1)

These warnings made me wonder...  Should I be using something that is more knowledgeable about the underlying device?  Can I force the arithmetic to 8bit?  Should I bite the bullet and use a megafunction (and lock myself into the IP) or is there some more portable middle-ground?

Apologies for the newbie question!

AK6DN:
The warning is referring to the unsized constant "+1" you are using, it will be inferred as 32b by default.
So you are adding two 8b values and a 32b value and storing an 8b result. Thus the (innocuous, usually) warning.
If you want change the "+1" to be a sized value, like "+8'd1" to make it an 8b decimal 1.
Or just ignore the warning.

NivagSwerdna:
That fixed it!  Thanks!

PS
I could probably squeeze an extra LUT by going proprietary but I have spare.  Much nicer to be more portable.

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