Electronics > FPGA

How to convert a 16-bit unsigned to 16-bit signed for multipliers

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coppice:

--- Quote from: radiolistener on October 14, 2024, 11:50:47 am ---
--- Quote from: coppice on October 14, 2024, 11:37:42 am ---Its more accurate to say you are removing signal rather than adding noise.

--- End quote ---

I disagree. When you truncate bits without rounding, the truncation error is signal-dependent and introduces a random error, which is effectively added noise. Rounding helps to minimize the amplitude of this noise by providing a more controlled error.

When I added rounding to the DSP of my SDR receiver, its spurious performance improved significantly. I noticed that some high spurs disappeared completely, while others were greatly reduced.

--- End quote ---
Sure, but if you had dithered instead of rounding you would have had a hard time finding any signs of those spurs at all, and yet you would have added around 1/2 a bit of noise to the signal.

radiolistener:

--- Quote from: brucehoult on October 14, 2024, 11:51:50 am ---What is the 16 bit unsigned binary number for 65534?

What is the 16 bit signed binary number for -2?

--- End quote ---

Both are 16’b1111111111111110 = 16'hfffe

The difference lies in how these numbers are mapped to signal amplitude within the ADC. Therefore, it is important to consider the format in which the ADC transmits data and to perform the necessary conversions if your code operates with a different representation.

In a signed representation, the number 0 corresponds to the center of the ADC scale, which roughly aligns with the average signal level. In contrast, for an unsigned representation, the number 32768 corresponds to the center of the ADC scale.

As you can see unsigned number 0 is not equals to signed number 0 in context of ADC output format.

In reality, the situation is a bit more complex since there is no specific code that represents the center of the scale due to the even number of codes. However, for the sake of simplicity in processing, the AES17 standard considers the signed number 0 as the center of the ADC scale. While this results in an asymmetrical scale, it simplifies the signal processing, and the value -32768 in this standard is considered as exceeding full-scale, because 16-bit full scale of signed number range is assumed as -32767..+32767.


To make it more clear, here is table with numbers for 4-bit ADC.
1-st column is a signal value in signed decimal format (which is used for processing)
2-nd column is a hex ADC output with unsigned format
3-rd column is a hex ADC output with signed format


--- Code: ----8 0 8
-7 1 9
-6 2 a
-5 3 b
-4 4 c
-3 5 d
-2 6 e
-1 7 f
+0 8 0
+1 9 1
+2 a 2
+3 b 3
+4 c 4
+5 d 5
+6 e 6
+7 f 7

--- End code ---



--- Quote from: coppice on October 14, 2024, 11:56:06 am ---Sure, but if you had dithered instead of rounding you would have had a hard time finding any signs of those spurs at all, and yet you would have added around 1/2 a bit of noise to the signal.

--- End quote ---

I understand what you're saying, but I'm not sure this approach can yield the same effective results as rounding. Dithering might be preferable if random noise is more acceptable than stable spurs, but it depends on the specific requirements of the application.

MarginallyStable:
If the ADC output is linear, I.E:
  0x0000 -> -5V
  0x8000 -> 0V
  0xFFFF  -> ~5V (-1bit value)

You just exclusive-or the MSB to get a signed value

   0x0000 ^ 0x8000 -> 0x8000 (most negative value signed value)
   0x8000 ^ 0x8000 -> 0x0000
   0xFFFF ^ 0x8000 -> 0x7FFF (most positive signed value)

EDIT: Just saw you mention unipolar

gael:
16-bit unsigned needs to get to 17-bit as signed, with a zero MSB added.

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