Author Topic: FPGA Verilog Project - Saving values for future processing  (Read 2676 times)

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Offline Razvan1203Topic starter

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FPGA Verilog Project - Saving values for future processing
« on: April 12, 2024, 09:09:48 am »
Hello everyone!

I'm currently working on a project where I have 2 seperate circuits. One with MSP430 that has an ultrasonic sensor that capture motions and the other one with an FPGA board Nexys A7 100T with a display that displays the exact time at which the motion was detected. Both circuit are communicating via Bluetooth with the help of 2 Pmod BLE modules.

My question is: How can I save those clock times when the motion was detected for future purpose? I mention that I also made a digital clock so the clock is not the problem. I want that after a whole day of motion detection, I can access those clock values stored somewhere and process them elsewhere. How can I do this?

Any answer or advice to my question is welcome! Thank you!
 

Offline BrianHG

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #1 on: April 12, 2024, 10:05:05 am »
Would a register array do?

reg [7:0] memory_array [0:63] ; // A 64 addressable block of 8 bit memory.
or
reg [31:0] memory_array [0:63] ; // A 64 addressable block of 32 bit memory.

input  write_data_ena;
input [5:0] 6_bit_read_address, 6_bit_write_address;
input [7or31:0] data_to_be_stored;
output reg [7or31:0] read_data_from_memoryy;


Replace reg with logic for system verilog.


if (write_data_ena) begin
     memory_array[6_bit_write_address] <= data_to_be_stored;
end


read_data_from_memory <= memory_array[6_bit_read_address];

Or, do you mean something else?
 

Offline xvr

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #2 on: April 12, 2024, 02:14:35 pm »
>  I want that after a whole day of motion detection, I can access those clock values stored somewhere and process them elsewhere.

I guess that you want not only record times but also provide some control for user to move through saved times. But Verilog not a best language to implement User Interaction.
I think that best option will be implement MicroBlase in FPGA and let all task for user interaction and time storage to it.
 

Offline BrianHG

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #3 on: April 12, 2024, 07:13:38 pm »
>  I want that after a whole day of motion detection, I can access those clock values stored somewhere and process them elsewhere.

I guess that you want not only record times but also provide some control for user to move through saved times. But Verilog not a best language to implement User Interaction.
I think that best option will be implement MicroBlase in FPGA and let all task for user interaction and time storage to it.
We cant be sure, he may have 1meg of blockram being unused.
He might also only need if ther is an event every second during the day being stored, so we are talking about 86400 1bit words, IE: 86kbit blockram.  Very easy for 17bit address.  If he wants only every second second resolution, 43k 1 bit words blockram.  Or, he may go for 172kbit having 48 hours of storage, 1 for downloading yesterday, the other for today's working buffer.

Adding an additional registered input controls & always (posedge clk) to my example code above will at least get Quartus/Xilinx/Lattice to auto instantiate that portion of the code into block ram without any FPGA vendor specific code/module/library making it cross compatible across almost all FPGA vendors.

« Last Edit: April 12, 2024, 07:59:03 pm by BrianHG »
 

Offline xvr

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #4 on: April 12, 2024, 07:16:59 pm »
Of course he can store all data in BRAM, but what he will do with this data next?
 

Offline BrianHG

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #5 on: April 12, 2024, 07:28:17 pm »
Of course he can store all data in BRAM, but what he will do with this data next?

Well, according to 'Razvan1203'

I want that after a whole day of motion detection, I can access those clock values stored somewhere and process them elsewhere. How can I do this?

Hmm, well, If the MSP430 was doing the detecting, I would have it hold the times of motion detection, but Razvan has the clock in the FPGA.  He might be downloading the BRAM table to another device through his BLE modules, we don't know.

We also don't know what's entailed in this processing.  It could be nothing more than a histogram over time.  I know this is a dumb thing to do in an FPGA unless you are doing millions of samples per second and want a live video graphic, like a digital oscilloscope, but a tiny simple MCU could probably do the basic if all you need is a day-to-day computation.
 

Offline antercreeper

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Re: FPGA Verilog Project - Saving values for future processing
« Reply #6 on: April 13, 2024, 04:10:51 am »
I have heard some lighter CPU cores 8)
For example the tinyrv32. ;)
 


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