Electronics > FPGA

How to design UART peripherals IP?

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antercreeper:
(I have read some method of oversampling, but well, I hate this methodology......)(I am very unhappy about these async things(mismatching over baud rates, clock jitter, etc...:palm:) )...... I would rather does with I2C or SPI. :(
So how to achieve clock synchronizing over UART?(like the serdes's clock data recovery?)
maybe need some analog things ::)(achieve some phase moving?) instead of RTL? (means that you need to pay some $ while making ASICs instead of working over FPGAs)

mtwieg:
UART is fundamentally asynchronous. Adding clock recovery wouldn't make it a better UART, but something else entirely, and I would not expect it to work any better with "standard" UART devices. If both sides are FPGAs which you have control over, then by all means do something fancy like adding NRZ or 8b/10b encoding. But if both sides were FPGAs then I doubt you would be stuck with UART to begin with.

Besides, UART is generally as reliable synchronous interfaces like I2C/SPI so long as the baud rates of the two devices are well-matched. Baud rate will likely be slower than SPI though. But sometimes the application calls for a true full-duplex connection.

ejeffrey:

--- Quote from: antercreeper on April 10, 2024, 08:17:48 am ---(I have read some method of oversampling, but well, I hate this methodology......)(I am very unhappy about these async things

--- End quote ---

Honestly I suggest you just try to get over that.  Oversampling is not the only way to implement a UART receiver but it's almost always the best.  Or you can design a synchronous protocol but then it's not UART and can't communicate with a UART peripheral.

Note that in some implementations SPI slave peripherals especially in FPGAs use oversampling as well.  They don't clock their internal logic with the SPI clock but instead treat it as data input to a higher speed state machine.

BrianHG:
Example Verilog UART.
Runs on 1 system clock.
Oversamples.
Also generates synchronizing TX output for high speed PC full duplex com.
Read and see documentation.

See here: https://www.eevblog.com/forum/fpga/verilog-rs232-uart-and-rs232-debugger-source-code-and-educational-tutorial/

(Skip the debugger part, you don't need that..)

langwadt:
the over sampling in a regular uart does effectively do clock (phase) recovery, it is just rather coarse with only 16x/8x because no more is needed.
Classic full speed USB usually does it with 4x oversampling

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