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How to have a reset signal for a Sipeed/Tang verilog design?
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Topic: How to have a reset signal for a Sipeed/Tang verilog design? (Read 2257 times)
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zapta
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How to have a reset signal for a Sipeed/Tang verilog design?
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December 29, 2024, 04:31:39 am »
I would like to program Sipeed Tang 4K in verilog and am not sure where to get the system reset signal that resets the entire design. Does the FPGA or the board provide such signal? If not, can I implement it myself?
The board documentation and schematic are here:
https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.html
On an Latice ice40 board I implemented a reset generator, based on the fact that all registers start at zero state. Can I assume the same about the Gowin FPGA?
https://github.com/FPGAwars/apio-examples/blob/master/examples/alhambra-ii/bcd-counter/reset_gen.v
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vagran
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Re: How to have a reset signal for a Sipeed/Tang verilog design?
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Reply #1 on:
December 29, 2024, 03:28:03 pm »
I did not check for Tang, but many FPGAs synthesize `initial` block where you can explicitly assign initial values to registers.
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zapta
zapta
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Re: How to have a reset signal for a Sipeed/Tang verilog design?
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Reply #2 on:
January 06, 2025, 05:42:53 am »
I ended up implementing this.
https://github.com/FPGAwars/apio-examples/blob/11826b8addc47cce8d84ab612eab4077feef5e73/examples/sipeed-tang-nano-9k/blinky/blinky.v#L9
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