Electronics > FPGA

How to pipeline DSP48 input?

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notooth:
I got this warning in Vivado. Can anyone tell me how to fix?

--- Quote ---DPIP #1 DSP design_1_i/add_tlast/inst/sa_tlast_out1 input design_1_i/add_tlast/inst/sa_tlast_out1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
--- End quote ---

asmi:
Add pipeline registers in front of/to the output of DSP?

notooth:
Yes, I think so.

hamster_nz:
If the design meets timing, then don't bother.

Otherwise add a set of pipelining registers to what is being multiplied, and cross fingers that the tools match the pattern and pull the pipelining registers into the DSP block.

notooth:
The design failed timing. Can you send me a tutorial or an example of non-pipelining registers and pipelining registers?

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