I'm messing around with some asynchronous FIFOs where the clock for the write side comes from an external pin (PAD) and the read side comes from an MMCM. The input to the MMCM comes from an external pin.
clk_wiz_0 MmcmPllThing(
.clk_out1(Clk)
,.locked(Locked)
,.clk_in1(RefClk)
);
There seems to be some magic with the clock wizard in that I get a complaint if I use a create_clock for the input to the MMCM (RefClk) saying that this clock is already defined. So, I assumed there is also something with the output since the timing engine knows what frequency the system clock is running at when doing a simple design that only uses the MMCM output.
I defined the FIFO write clock with:
create_clock -period 100.000 -name ExtWrClk [get_ports ExtWrClk]
When I try to reference the MMCM output for set_false_path or for set_clock_groups using [get_clocks Clk], I get failures about the clock unless I use:
set_false_path -from [get_clocks ExtWrClk] -to [get_clocks clk_out1_clk_wiz_0]
This upsets the Synthesis phase but makes the Implementation phase happy and gets rid of the timing violations (seems to work).
What is the correct way to get the output of the MMCM to the synthesis phase that also works into the implementation phase?
I did not have luck creating a clock named Clk using create_clock.
P.S. I got to learn about the need to send a clock into the FPGA on a "Clock Capable Pin" (MRCC or SRCC using the P version for single ended).