Electronics > FPGA

How to set base address in Vitis / Vivado??

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Mario87:
Hi all, I have a project that I have been working on for a while that uses a MicroBlaze CPU with address range 0x00000000 to 0x0003FFFF (256KB) and RAM with address range 0x80000000 to 0x9FFFFFFF (512MB).

With the project I can create the download.bit file in Vitis from the Vivado generated .bit file and the .mmi file if I have the processor to only initilise on bootloop at startup and not an actual ELF file. Then I can kick off the code manually from within Vitis.

I now want to include the ELF file within download.bit so that I can run from a MicroSD and as soon as it loads the MicroBlaze program kicks off, but when I try to do that I get the error below...


--- Quote ---\Vitis\xv_procss_example_2\Debug\xv_procss_example_2.elf is mapped to address range [80000000:80034BEB], but there is no memory available in that range. Make sure that the data file base address is set to an address corresponding to the memory address range in the design.
--- End quote ---

The address range is for the DDR memory, where as it should be for the MicroBlaze Local RAM (0x00000000 to 0x0003FFFF)....how can I update the 'data file' (as it says) to set the correct base address to 0x00000000 instead of 0x80000000?

Thanks!

asmi:
Find a linker script in the project tree (typically in "src" folder, called lscript.ld), double-click it, and you will see all sections and which address space they go to. Each line there is a combo-box where you can select any address space which is declared in your BSP as a type of "memory". See attached screenshot for details.

Also remember that once you compile your binary, you will need to "integrate" it into the bitstream. And you will have to do it every time you make any code changes - unless you run the code directly through Vitis - in which case Vitis will take care of it for you.

Mario87:

--- Quote from: asmi on June 08, 2023, 07:41:04 pm ---Find a linker script in the project tree (typically in "src" folder, called lscript.ld), double-click it, and you will see all sections and which address space they go to. Each line there is a combo-box where you can select any address space which is declared in your BSP as a type of "memory"). See attached screenshot for details.

Also remember that once you compile your binary, you will need to "integrate" it into the bitstream. And you will have to do it every time you make any code changes - unless you run the code directly through Vitis - in which case Vitis will take care of it for you.

--- End quote ---

Awesome, that has sorted it thanks!  :-+

asmi:

--- Quote from: Mario87 on June 08, 2023, 10:22:15 pm ---Awesome, that has sorted it thanks!  :-+

--- End quote ---
You are most welcome!
Just a word of caution - debugging firmware running from BRAM is very tricky as debug builds are typically much larger than release ones, and BRAM space is typically very limited, so if your board has some kind of external memory, it's best to use it during debugging even if you don't intend to use it for the final build - it will make your life a lot easier.

The way I design most of my firmware is that I include a small bootloader into the BRAM which loads the main application from spare space in the QSPI flash into DDR and then launches it. Xilinx includes a template for such bootloader with Vitis, but it's not very hard to develop one by yourself. There is also an option to set QSPI flash as XIP and run it directly, but you will need to remember than XIP address space is read-only and so you will need to remap all non-readonly sections into some other address space. I personally never tried that, but it sounds like an interesting way to save some memory if you are short of it. The advantage of both those approaches is that there is virtually no limit for the firmware size (within reason of course, as long as it fits within spare space of QSPI flash, but that's usually are few MBytes), and you don't actually need to burn into the flash debug versions as Vitis can copy them into DDR directly for you.

Mario87:
Thanks for the info, I have however noticed that as a minimum, the ones listed as 'MicroBlaze_MCU.....' in the image attached need to be in BRAM otherwise I get the same error above about the base address being wrong.

I cannot put all of them in the 256K of BRAM in my design otherwise it says there is not enough space (approx 95K short) and if I increase to 512K of BRAM in Vivado it totally messes up the timing.

Is it possible to force them all to run off of DDR and not throw up that error relating to the base address being wrong? Or as a minimum to I have to keep the 256K of BRAM in my design and run these from the MicroBlaze with base address 0x00000000?

Just that I am developing on an Artix 7 Series XC7A200T FPGA at the moment on a dev board and it looks like if I can limit the BRAM usage then I could probably fit this onto an XC7A50T in the final design, but the BRAM availability on the XC7A50T is just 75x 36Kb blocks vs the 365x 36Kb blocks available on the XC7A200T (of which I am using ~235, but also with ILAs and other devices which I will remove in the final design).

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