Electronics > FPGA

How to use FIFO to process fast ADC data

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miken:
This must be something really wild if you have an RFSoC, need more ADC, and can't use SERDES. But realistically, when using fast data converters you need to pick your FPGA to meet the interface requirements of the ADC/DAC. If you can't use JESD204x then you need a lotta pins and careful clock planning.

asmi:

--- Quote from: ejeffrey on August 11, 2022, 04:35:10 pm ---Also I should add: 2 Gbit/s is faster than most FPGAs can operate their LVDS IOs.  AFAIK both the Xilinx Ultrascale+ and Intel 10 series FPGAs max out at 1.6 Gb/s.

--- End quote ---
That's not strictly true. Ultrascale+ has MIPI which can go as fast as 2.5G, and it technically is LVDS (only with smaller Vdiff and offset).

dut:Mark:
As you are on a Gen1 RFSoC, you could take a look at the resources for the ZCU111 evaluation board. UG1287 and the accompanied download (rdf0476-zcu111-rf-dc-eval-tool-XXXX-X.zip) contains reference designs which you can have a look at for inspiration. The design contains FIFO's for recording and playback, which are emptied or filled respectively by a DMA controller from/to the PS memory.

Keep in mind that you end up with quite a large bandwidth for 16x16 converters at 250 MHz complex baseband (assuming 8x interpolation/decimation for the RFDC IP). Probably the reason that the later RFSoC devices have added additional interpolation and decimation options to choose form.

Imho, conceptually there is no difference between interfacing over AXI-Stream with the RFDC-IP for data, or a JESD interface IP for an external data converter connected by serial transceiver(-s)? Just in case of the RFSoC, you don't have to bother with getting the JESD interface up and running.

tom66:
You can definitely go beyond the raw specification of the SERDES input on most FPGAs provided you're careful with your input delay training.  For instance the Zynq 7010 is 950Mbit/s rated in speed grade -1 but I had it reliably up to 1.4Gbit/s for input and 1.6Gbit/s for output (in the output case you can insert an ODELAY on the clock or data to shift either into the eye.)

The trick is doing this without having a 10GHz scope to test it...!

BrianHG:

--- Quote from: tom66 on August 12, 2022, 12:48:31 pm ---The trick is doing this without having a 10GHz scope to test it...!

--- End quote ---
LOL, some ADC have a test pattern output for eye alignment.  Using such a pattern feature built into DDR3 ram chips DQ port, my DDR3 controller aligns what supposed to have a 600mb serdes IOs limit running fine at 1ghz.  Though, the code is involved and if you are lucky, the ADC may have I2C registers to set this up and tune there so you do not have to work out how to tune your FPGA's PLL like I did with my controller.

     Just so we are clear, it's my HDL which does this measurement at power-up and aligns for the best error free 'center tuning' of the data coming in before continuing on with the rest of my design.  This tuning procedure is done every system wide power-up and reset.

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