You definitely need a SERDES. Keep in mind that there are two types of SERDES in most FPGA. There first are the multi gigabit transceivers used for high speed serial interfaces like PCIe, USB3, and JESD204b. These used dedicated IO pins and clocks, and are not what you want unless your ADC uses JESD204b. The other is a simple IO SERDES. These are intended for medium speed parallel interfaces on mostly regular IO pins (with some restrictions) using either LVDS or single ended signalling and often DDR. They are commonly used for DRAM and for parallel DACs and ADCs. They have a configurable serdes ratio to allow stepping down from the IO frequency to something suitable for the FPGA fabric. What exact features are supported and the way you instance this depends on your specific FPGA family.
You may also need a FIFO. A FIFO can be used to handle clock domain crossing and can also have different input and output widths. However the FIFO is built into the FPGA fabric and both ends of it must operate with a clock that can be used within the FPGA fabric. Realistically that means less than 500 MHz, often a lot less depending on your FPGA and what logic you need. Again, the way you instance this depends on your FPGA toolchain. Look through their selection of IP blocks and look for a dual clock FIFO and see what the options are.