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How to use FIFO to process fast ADC data

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knight:
Hello. I have to interface a fast 16-bit ADC with a slow clock FPGA. I cannot use SERDES block. So, the only option is to use FIFO. The ADC clock (lets say 2GHz) is "8x faster" than the FPGA clock (lets say 250MHz), I have only this information known to me. Can anyone point me to some sources if this has been done before or can give an idea as to how to use a FIFO in this case?
Thank you.

nctnico:
AFAIK the only option is to use some kind of SERDES IP. A FIFO won't do you any good because this doesn't change the data rate. You need to go from a narrow & fast path to a wide & slow path. Even 250MHz is quite fast for an FPGA if you need to have large amounts of logic to deal with the data.

ejeffrey:
You definitely need a SERDES.  Keep in mind that there are two types of SERDES in most FPGA.  There first are the multi gigabit transceivers used for high speed serial interfaces like PCIe, USB3, and JESD204b.  These used dedicated IO pins and clocks, and are not what you want unless your ADC uses JESD204b.  The other is a simple IO SERDES.  These are intended for medium speed parallel interfaces on mostly regular IO pins (with some restrictions) using either LVDS or single ended signalling and often DDR.  They are commonly used for DRAM and for parallel DACs and ADCs.  They have a configurable serdes ratio to allow stepping down from the IO frequency to something suitable for the FPGA fabric.  What exact features are supported and the way you instance this depends on your specific FPGA family.

You may also need a FIFO.  A FIFO can be used to handle clock domain crossing and can also have different input and output widths.  However the FIFO is built into the FPGA fabric and both ends of it must operate with a clock that can be used within the FPGA fabric.  Realistically that means less than 500 MHz, often a lot less depending on your FPGA and what logic you need.  Again, the way you instance this depends on your FPGA toolchain.  Look through their selection of IP blocks and look for a dual clock FIFO and see what the options are.

ejeffrey:
Also I should add: 2 Gbit/s is faster than most FPGAs can operate their LVDS IOs.  AFAIK both the Xilinx Ultrascale+ and Intel 10 series FPGAs max out at 1.6 Gb/s.  There may be some exceptions: I haven't looked at the highest end parts and they may be able to go faster when using hard memory controllers.  >1 GS/s DACs and ADCs typically have a built in 2:1 or even 4:1 mux (or use JESD204b).  So a 2 GS/s 16 bit ADC would have a 32 bit data bus and send 2 samples per transfer.  These chips may have the MUX be optional.  However, you will not be able to run them at the full data rate without it, at least on most FPGAs you are likely to use.

knight:

--- Quote from: ejeffrey on August 11, 2022, 04:35:10 pm ---Also I should add: 2 Gbit/s is faster than most FPGAs can operate their LVDS IOs.  AFAIK both the Xilinx Ultrascale+ and Intel 10 series FPGAs max out at 1.6 Gb/s.  There may be some exceptions: I haven't looked at the highest end parts and they may be able to go faster when using hard memory controllers.  >1 GS/s DACs and ADCs typically have a built in 2:1 or even 4:1 mux (or use JESD204b).  So a 2 GS/s 16 bit ADC would have a 32 bit data bus and send 2 samples per transfer.  These chips may have the MUX be optional.  However, you will not be able to run them at the full data rate without it, at least on most FPGAs you are likely to use.

--- End quote ---
The FPGA is Zynq Ultrascale+ RFSOC ZU29DR.

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