I don't understand MachXO2 programming mechanism

[soFPG]

I am planning to use a MachXO2 1200HC 6SG32C and therefore make myself familiar with how programming is done.
Unfortunately, I am really confused by the "MachXO2 Programming and Configuration Usage Guide".

There are INIT, PROGRAMN and DONE pins. The first reason why I am confused is because "INIT" pin is not available on my QFN-32 package but the usage guide continues to mention the INIT pin as if I have to do something with it while it is not even accessible for me?
Second, PROGRAMN - how do I use it? If I understood correctly, I have to drive it low via a button to enable programming via JTAG? Is this correct?

My idea was to connect a LED to DONE pin such that I get a visual feedback once programming is complete (current schematic attached below).

Feedback is very much appreciated.

[SiliconWizard]

IME, all of those pins can be left floating on MachXO2 devices in the default configuration. JTAG is enabled by default, I don't remember how you use JTAGENB, but I sure left it NC on my boards and never had a problem. I actually left ALL of the pins you mentioned NC, and it's OK for JTAG configuration.

Not sure what the DONE pin would give you here if it's just for visual feedback. The programmer itself will give you feedback when Flash programming is done. Then, MachXO2 devices are fully configured (ready to work) in just a few ms from Flash (as opposed to some FPGAs using external Flash, which can take hundreds of ms), so the visual feedback would not serve much purpose IMO.

The above pins are probably to be considered in cases where you want to use other means of programming on top of JTAG (SPI...)

I (very briefly) re-read the MachXO2 programming guide, and it looks like the usage of the above pins is described in it. Not just in one place though (a bit spread out), so you'll need to search for the pin names in the PDF to get what purpose they serve.

[soFPG]

Are you sure about that? Your report about not using any of those pins just makes it even more apparent for me that I didn't understand that Usage Guide ( http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/MO/MachXO2ProgrammingandConfigurationUsageGuide.ashx?document_id=39085 ) 

visual feedback would not serve much purpose IMO.

At least I know the current state without having to probe for the DONE pin with a continuity test. That's how I thought about it.

[SiliconWizard]

Are you sure about that? Your report about not using any of those pins just makes it even more apparent for me that I didn't understand that Usage Guide ( http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/MO/MachXO2ProgrammingandConfigurationUsageGuide.ashx?document_id=39085 ) 

Pretty sure, yes. Can you quote one specific part in it that would make you think otherwise?

Just for the JTAGENB pin here, for instance:

The JTAGENB pin is only available when the JTAG_PORT is in the DISABLE state.

MachXO2 devices certainly don't ship with JTAG disabled by default. You have to explicitely do this with a special configuration.

As an example, you can take a look at the schematic of the MachXO2 breakout board from Lattice. Those pins are broken out on PCB pads, but left open, and you don't need to fiddle with those to be able to use the board whatsoever.

visual feedback would not serve much purpose IMO.

At least I know the current state without having to probe for the DONE pin with a continuity test. That's how I thought about it.

This would be useful only if the device is blank, thus internal Flash has never been programmed before. Otherwise, as I said, it will be configured within a couple ms after power on, thus probing the pin is kinda useless. Sure if you want a simple means of seeing whether a given board has a blank FPGA or not, then OK, why not. As I got it though, the DONE pin is bidirectional with a weak internal pull-up, I and is active high; I wouldn't tie it directly to a LED, but through a MOSFET preferably.

[soFPG]

Can you quote one specific part in it that would make you think otherwise?

This section on page 4 reads like as if I have to something with these pins

The FPGA remains in the initialization state until all of the following conditions are met:
• The tINITL time period has elapsed
• The PROGRAMN pin is deasserted
• The INITN pin is no longer asserted low by an external master

As an example, you can take a look at the schematic of the MachXO2 breakout board from Lattice. Those pins are broken out on PCB pads, but left open, and you don't need to fiddle with those to be able to use the board whatsoever.

Thank you for the hint, I guess I'll orientate my own design on it.

[SiliconWizard]

Can you quote one specific part in it that would make you think otherwise?

This section on page 4 reads like as if I have to something with these pins

The FPGA remains in the initialization state until all of the following conditions are met:
• The tINITL time period has elapsed
• The PROGRAMN pin is deasserted
• The INITN pin is no longer asserted low by an external master

Both pins have internal weak pull-ups and can be left floating, the standard initialization sequence at power-on will work fine.
Asserting them low from the outside serves special purposes (you can re-trigger an initialization sequence for instance), but you don't need to use them in the standard use case. Both pins are active low, and have internal pull-ups, so by default they are NEVER asserted.

[TimCambridge]

My idea was to connect a LED to DONE pin such that I get a visual feedback once programming is complete.

Don't do that. You will effectively pull DONE low - programming stalls when DONE is Low. Put your LED on another pin.