ice40 HX, A 5v tolerant FPGA ??

[woofy]

Well this is curious. I'm interfacing a PS2 keyboard to an ice40 HX8k and I needed to protect the 3.3v inputs from the 5v PS2 signals. The PS2 appears to have 2k2 pull-ups as I get about 2.2mA shorting clk or data to ground. So I thought I'd add additional 1k8's in series with the signals and let the ESD diodes do the clamping for me. Imagine my surprise when I looked on the 'scope and still saw 5v signals on the FPGA inputs! It works too, as I can echo the signals out on other pins. It seems as though there are no input protection diodes, or maybe there are and they clamp to 5v. The HX data sheet is clear, 3.6v absolute Max. I did a little poking around on the web and found the ice40 was acquired by Lattice from Silicon Blue, and Silicon Blue's previous ice65 ~was~ 5v tolerant.
So I'm thinking maybe the ice40 is 5v tolerant, at least the HX8k.
Does anyone know for sure?

Maybe I'll see the magic smoke at some point, but hey, its a hobby project.

 

[asmi]

You are free to try of course, but I'm 99% certain you will blow an IO buffer, or maybe the entire IO bank (depending on how it's wired internally). The fabric will probably survive because it's typically in a separate voltage domain than IO blocks, but who cares about it if you can't do any IO?

[woofy]

Well, I've done a few more tests, feeding a higher voltage onto the HX8k pins via a 47k resistor.
At 5v input there is no current draw. The voltage is the same both sides of the resistor.
At 6v it is still almost 6v on the pin and its pulling 550nA.
At 6.5v it has 6.35v on the pin
7v gives 6.38v on the pin.
8v, 6.39v
9v, 6.39v
10v, 6.4v
20v, 6.41v

This is the same across every random pin I checked.
It seems the HX8k has an avalanche FET clamp rather than the expected diode to VCCIO, clamping at 6.4v.
The only reason for this that makes any sense is that this is a 5v tolerant device, designed that way by Silicon Blue.

I think for Lattice this is an unwanted feature they don't include in their other devices and don't want to cloud the range by having mixed tolerance devices.

[nonarkitten]

I just wanted to say thanks for this discovery. We'll test this out some more, but if the original generation of iCE40's are in fact still 5V tolerant, then that's just amazing news.

[SiliconWizard]

How much current does it draw @20V?

[nonarkitten]

Ohm's laws says about 0.29mA at 20V.

[SpacedCowboy]

So this is sufficiently intriguing to be worth exploring a bit. I'm happy to try it out on a long-term test and see if the magic smoke appears, but it's only useful to me if the rise-times of the resistor-assisted lines are sufficiently fast. Not entirely sure I'm doing the right calculation here, but does the below make sense for a test scenario ?

Assuming 8 mil trace width, on a stack-up as in the image with 0.12mm between the top and next-plane (GND), Saturn tells me I get a trace capacitance of 9.7085 pF/cm. Let's say I have a nominal trace length of 5cm.

Using the rise-time equations on the Wiki RC constant page, I get a resistance of ~47R for a 5ns rise-time. If I get some 1206, 1/4W resistors that would seem to be fine.

This seems a little easy, so (apart from the fact this is probably going to blow up my FPGA, which I'm good with), what else am I missing / have got wrong ?

[DiTBho]

It seems the HX8k has an avalanche FET clamp rather than the expected diode to VCCIO, clamping at 6.4v.

The only reason for this that makes any sense is that this is a 5v tolerant device, designed that way by Silicon Blue.

I think for Lattice this is an unwanted feature they don't include in their other devices and don't want to cloud the range by having mixed tolerance devices.

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

[woofy]

Not entirely sure I'm doing the right calculation here,

What I was suggesting is that 5v logic can be connected directly to iCE40 HX8K inputs, no resistors.
My use of a 47k resistor was just to protect the FPGA whilst I applied voltages up to 20v to see where it clamped.

[woofy]

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

This is a guess, but I suspect the avalanche FET clamp requires a non-trivial amount of silicon to implement. The input diodes to vcc are intrinsic (parasitic) devices, a bit like the reverse diode in a mosfet. That and there is probably near zero commercial demand as level translators can be used when 5v interfacing is required.

[Forty-Bot]

What bank did you use for testing? The ice65 only supported 5V inputs on banks 0, 1, and 2. In particular, bank 3 was 3V3 only. I wonder if the same restrictions apply here.

[SiliconWizard]

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

This is a guess, but I suspect the avalanche FET clamp requires a non-trivial amount of silicon to implement. The input diodes to vcc are intrinsic (parasitic) devices, a bit like the reverse diode in a mosfet. That and there is probably near zero commercial demand as level translators can be used when 5v interfacing is required.

Yep. Guys stuck in the "vintage world" tend to think that their world is significant, but this is just a very small niche.
And level translators are plenty and cheap.

Not to mention that actually clamping to voltage rail with a simple diode is often the more desirable behavior.

[langwadt]

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

This is a guess, but I suspect the avalanche FET clamp requires a non-trivial amount of silicon to implement. The input diodes to vcc are intrinsic (parasitic) devices, a bit like the reverse diode in a mosfet. That and there is probably near zero commercial demand as level translators can be used when 5v interfacing is required.

Yep. Guys stuck in the "vintage world" tend to think that their world is significant, but this is just a very small niche.
And level translators are plenty and cheap.

Not to mention that actually clamping to voltage rail with a simple diode is often the more desirable behavior.

and the transistors used might not able to handle 5V. I've used a Xilinx FPGA where LVDS output just goes tristate when the IO voltage goes above ~2.9V, asking Xilinx about I was told it was a safety feature disconnection the LVDS drivers to prevent you from configuring LVDS outputs in a 3.3V powered bank because it would damage the part

[DiTBho]

Not to mention that actually clamping to voltage rail with a simple diode is often the more desirable behavior.

why? a diode is more noisy

[Someone]

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

This is a guess, but I suspect the avalanche FET clamp requires a non-trivial amount of silicon to implement. The input diodes to vcc are intrinsic (parasitic) devices, a bit like the reverse diode in a mosfet. That and there is probably near zero commercial demand as level translators can be used when 5v interfacing is required.

Xilinx talks about the challenges in their (very old) XAPP311

When a silicon vendor offers a 5V tolerant part, the design group will put additional circuitry into each I/O cell to allow the pin, when used as an input, to go above the 3.3V VCC rail. This circuitry can be fairly complex, typically involving more than a dozen transistors.

.. and gets more complex/expensive from there.

[DiTBho]

to guaranty fast charge/discharge of the gate' Mos CoX capacitance?

[julian1]

vccio for each gpio bank is documented to support 3.3 V2.5 or V1.8 to allow interfacing to different logic levels.

Would an experiment powering one of the gpio bank rails with 5V be worthwhile? On the chance the outputs can switch that voltage, and not just tolerate it as input? 

[SiliconWizard]

As langwadt already said, if the transistors used in the IO blocks are not designed to support 5V, they just are not and you're wasting your time. If that's the case though, powering the IO bank @5V is likely to be worse than powering it @3.3V and injecting 5V signals at the inputs.

Experiments are not going to do much except if you're ready to set up an experiment for a long time. While @5V you may not be able to damage the IOs in a short amount of time, the degradation may come after weeks or months of operation. There is no real way of knowing except having the detailed design of the chip, or just trusting the datasheet and add level translators. All I can say is that for a typical chip of this kind, on the typical CMOS processes used, most transistors will be rated for 3.9V-4V absolute maximum and going over this *is* going to degrade them. Adding transistors that can handle 5V (which would be about 6V absolute max.) either takes significantly more area (thus, more expensive dies) or even a different process node which is also likely to be more expensive.

Problem here is, we just don't know for sure what they did and validating that with just simple experiments is not that easy.

[julian1]

Looking at an old silicon blue datasheet - the 5V tolerant support using vccio 3v3 bank is clearly stated, while there is no mention of other higher voltages.

So yes, you're right, it makes no sense, to go outside the bound of what is documented by the original manufacturer (even assuming the same process support). i was thinking it wasn't certain what precise capabilities had been dropped from documentation when the ownership change.

[SiliconWizard]

I understand your point, I'm just not sure why Lattice would have dropped this feature if it was fully functional - AFAIK, it wasn't even directly competing against their own products? Don't think they had FPGAs with 5V-tolerant IOs? (Except maybe for their old PLDs which were definitely not comparable to the ice40 series?)

Point is, if they dropped it, it's either because it would have harmed sales of existing products, or because it was evaluated not reliable enough and thus not fit for commercial purpose?
Or did they just not want to have ANY 5V-tolerant part in their catalog for some odd reason? Just trying to find the rationale.

[SpacedCowboy]

> Or did they just not want to have ANY 5V-tolerant part in their catalog for some odd reason? Just trying to find the rationale.

About the only reason I could think of for that is that their marketing dept. didn't want them to be seen as "old fashioned" and "out of date". Seems like a pretty weak argument because "backwards compatible" is hardly a problem - but I guess 5v technology is now *really* old, so who knows.

Tbh, I agree it's a niche market, but it's a big world out there, I'm kind of surprised any chip vendor would remove any potential "we can do that" feature unless it just didn't work, as you say.

Still fine with running a long-term test. I have the FPGA board now, but the ancient computer is getting its RAM replaced. Once that's done I'll wire it up and let it run for a few months in the corner, with some sort of visual display that it's still both active at the core, and reading the GPIO @5v.

[SiliconWizard]

Yeah. Another reason could be that Lattice decided to use a slightly different process node to make those from what was initially used by SiliconBlue and possibly some parameters changed and could not guarantee reliability @5V.

[gekkio]

I think you might be jumping to a conclusion a bit too quickly...the lack of a simple protection diode to VCCIO does not mean the device is 5V tolerant. In fact, it seems like having no protection diode is the default in modern FPGAs. I went through the CPLD/FPGA datasheets I had saved locally, and collected their absolute maximum ratings for input voltages and checked if the datasheet mentioned a protection diode somewhere. None of the devices support true 5V VCCIO but some are defined to be 5V-tolerant when 3.3V VCCIO is used, as indicated by the max rating.

CPLDs:

• Xilinx Coolrunner-II: no diode, max 4.0V
• Xilinx XC9500XL: no diode, max 5.5V
• Lattice ispMACH 4000 V/B/C/Z: no diode, max 5.5V
• Lattice ispMACH 4000 ZE: no diode, max 5.5V
• Intel/Altera MAX II: no diode, max 4.6V
• Intel/Altera MAX V: no diode, max 4.6V

FPGAs:

• Xilinx Spartan-3E: has diode, max VCCIO + 0.5V
• Xilinx Spartan-6: no diode, max 3.95V
• Lattice iCE40 LP/HX/UL/UP/LM: no diode, max 3.6V
• Lattice iCE40 Ultra: no diode, max 3.6V
• Lattice MachXO2: no diode, max 3.75V
• Lattice MachXO3: no diode, max 3.75V
• Intel/Altera MAX 10: no diode, max 4.12V
• Intel/Altera Cyclone IV: no diode, max 4.2V
• Intel/Altera Cyclone V: no diode, 3.8V
• Intel/Altera Cyclone 10 LP: no diode, max 4.2V

So, based on this very quick investigation, only one of the devices (Spartan-3E) has I/O protection diodes to VCCIO, and it's from 2004. Some devices support a switchable clamp diode to VCCIO (for PCI I/O compliance?), but that depends on configuration and isn't always enabled. Just because some previous generation devices (iCE65) manufactured with an older process (65nm) had 5V-tolerant inputs in some banks, it doesn't mean the next generation has the same characteristics.

I don't know about the manufacture side of things, but the lack of a protection diode to VCCIO provides one practical advantage I didn't see mentioned yet: a normally valid high signal on an I/O while the CPLD/FPGA is powered off won't get shunted to VCCIO. This adds some flexibility to power sequencing and/or supporting multiple switchable power domains on a board, because you won't necessarily draw excessive current from the I/O pin of some other device even if you are outputting a valid high while the CPLD/FPGA is off. Just recently I encountered this with a design where I realized I made a mistake in power sequencing and was outputting a digital 3.3V signal to an unpowered iCE40 HX4K in certain scenarios. I panicked and thought I broke the other device and had to respin the board to avoid the problem, but I read the datasheet and even measured the current drawn by the iCE40 pin in this scenario to double-check it was safe: the current was 20 nA I've also intentionally used extra 74LVC buffers in some designs to safely isolate different power domains, because 74LVC doesn't have VCC protection diodes and doesn't get upset with normal I/O voltages in its inputs while unpowered.

Based on the available evidence, I'm almost certain that iCE40 HX is not 5V-tolerant, and if you exceed its maximum rating, you're going to break something over time. It might not be spectacular "smoke escapes device" kind of breakage, but maybe the gate oxide layer of the input buffer transistors break and you lose each pin that has suffered this overvoltage condition for some period of time. Not fun to debug if it happens! Remember also that gate oxide degradation is cumulative (and IIRC non-linear w.r.t the input voltage...?), so a single quick test is not enough if you care about the longevity of your device.

[DiTBho]

• Xilinx Spartan-3E: has diode, max VCCIO + 0.5V

I have to check what GBA-Xport used for their Nintendo GBA special cartridge.
I remember it was a Xilinx Spartan-3*-something, but I don't remember details.
I know, GBA is fully 5V, and there are no level shifters on the cartridge
      Nintendo SoC(z80 + ARM + bootstrap-rom + mem controller + PLL + basicIO)<--->FPGA
It was very expensive back in 2001 (200-250 Euro), hope to find one 

p.s.
thanks for the post! Really useful 

[DiTBho]

None of the devices support true 5V VCCIO but some are defined to be 5V-tolerant when 3.3V VCCIO is used, as indicated by the max rating.

• Xilinx XC9500XL: no diode, max 5.5V

this must be the reason why some vintage 5V projects specify in bold this

Parts list
...
Xilinx XC9536 CPLD – not XC9536XL

although XC9536XL is 5V tolerant, it only offers 3.3V or 2.5V  output capability.