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#### renzoms

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« on: October 26, 2019, 03:10:12 am »
This code works. The purpose of the code is so you can see I have an original 8-bit carry-look ahead adder Verilog file.

The images of my textbook, that I purchased, given advice on reddit, are so you can see where the text from which I am not understanding where certain gate delays of a second level carry-lookahead adder are...

The next exercise is to produce a second level carry-lookahead adder. The goal is 4 of these 8-bit carry-lookahead adders (CLA) to produce a 32-bit CLA. I know this CLA is four gate delays. The text claims the options are a ripple-carry design, or a second level CLA. *So the ripple-carry design would add 3 more gate delays for c8, c16, and c24 to ripple. So if c32 was important, a 4th gate delay (When is it important? I just use it for overflow detection, and it would be important in the case where I make this into a 64-bit adder). So the 32-bit adder should take should take 4 gate delays, plus 3 or 4 gate delays, plus 1 more for an XOR addition/subtraction control. 8 or 9 gate delays. Please correct me if I'm wrong.

So the second level carry-look ahead adder uses G and P. G is a two level AND-OR. And P is an AND gate. The equation is c8 = G + Pc[0]. Pc[0] requires one more AND gate. Here we are at two gate delays. Finally G + Pc[0] requires an OR gate so all of the carry bits are generated in three gate delays. So compared to our ripple-carry CLAs, which required four gate delays to produce carryout of the MSB, and then had to ripple, the second-level carry-lookahead adder requires 3 gate delays. The second level carry-lookahead adder is simultaneously processed as the CLA so the critical path delay is 4 gate delays, -- ok I need help here. The text says "Using this scheme, it takes two more gate delays to produce the carry signals c8, c16, c24, c32 than the time needed to generate the G and P functions. Therefore, since G and P require three gate delays, c8, c16, c24, and c32 are available after five gate delays." Where are these two more gate delays? And I need help here. The text says "The time needed to add 32-bit numbers involves these five gate delays plus two more to produce the internal carries in blocks 1, 2, and 3" Where are these two gate delays?

For my own sake: There are 4 gate delays to produce the sum bit and all carrybits within block 0, 1, 2, and 3. There are three gate delays to produce c8.

A whole different concern after those concerns: doesn't c8 ripple in Figure 3.17? It takes three gates to produce it and then it ripples for a total of four gate delays?
« Last Edit: October 27, 2019, 05:33:57 pm by renzoms »

#### rstofer

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« Reply #1 on: October 26, 2019, 09:08:50 pm »
Have you looked at the logic for the 74181 and 7418 devices?

Also, around page 43 here:
https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

Each FPGA design has a somewhat different slice design and Xilinx has optimized theirs with the carry chain.  I don't know what others have done.

Smf