Electronics > FPGA

Implementing old PAL/GAL into HDL

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caius:
Hi all,
I'm porting into Quartus some old schematics for CPLD/FPGA implementation.This old hardware made of TTL gates but there are also some PLDs (GALs and PALs) that I have fusemap of.Some of them are pure combinatorial logics and perhaps I know how to write a Verilog module (just matter of declaring the I/O and put equations for each output).But others PLDs are registered so they have sequential logics inside (a clock and an output enable pin).So, I'm looking for some help about.Thanks in advance for any tip/suggestion/example.

Bassman59:

--- Quote from: caius on July 28, 2021, 05:13:43 pm ---Hi all,
I'm porting into Quartus some old schematics for CPLD/FPGA implementation.This old hardware made of TTL gates but there are also some PLDs (GALs and PALs) that I have fusemap of.Some of them are pure combinatorial logics and perhaps I know how to write a Verilog module (just matter of declaring the I/O and put equations for each output).But others PLDs are registered so they have sequential logics inside (a clock and an output enable pin).So, I'm looking for some help about.Thanks in advance for any tip/suggestion/example.

--- End quote ---

I suppose you should learn how to design sequential circuits in Verilog.

caius:

--- Quote from: Bassman59 on July 28, 2021, 07:40:02 pm ---

I suppose you should learn how to design sequential circuits in Verilog.

--- End quote ---

Yes, obviously.But, as said,implementing a PLD with combinatorial logics is easy.Here's an example :


--- Code: ---module PAL16L8_U8(
input _MR, PIN14_U16, PIN13_U16, PIN12_U16, PIN19, PIN6_U12, PIN18,
output PIN12_U8, PIN23, PIN25, PIN22, PIN27, PIN17_U8, PIN18_U8,
   inout PIN19_U8);



assign PIN12_U8 = ~(_MR & PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12);
 

assign PIN23 = ~(_MR & PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12);
 

assign PIN25 = ~(_MR & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12);
 

assign PIN22 = ~(_MR & ~PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN6_U12);
 

assign PIN27 = ~((~PIN19_U8) |
       (_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12) |
       (_MR & PIN19_U8 & PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12));
 
assign PIN17_U8 = ~((PIN19_U8 & ~PIN14_U16 & ~PIN19) |
      (_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12) |
      (_MR & PIN19_U8 & ~PIN14_U16 & ~PIN13_U16 & PIN12_U16 & PIN19 & PIN6_U12));
 

assign PIN18_U8 = ~((_MR & PIN19_U8 & ~PIN14_U16 & ~PIN13_U16 & PIN6_U12) |
      (_MR & PIN19_U8 & PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12) |
      (_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12));
 

assign PIN19_U8 = ~(_MR & ~PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12 & PIN18);
endmodule
--- End code ---


Here's, instead, the disassembling of a registered PAL which I would like to port to Verilog (or VHDL) :

 
 


--- Code: ---/** Inputs **/
Pin 2 = i2;
Pin 3 = i3;
Pin 4 = i4;
Pin 5 = i5;
Pin 6 = i6;
Pin 7 = i7;
Pin 8 = i8;
Pin 9 = i9;
Pin 12 = i12;
Pin 13 = i13;
Pin 14 = i14;
Pin 15 = i15;
Pin 16 = i16;
Pin 17 = i17;
Pin 18 = i18;
Pin 19 = i19;

/** Outputs **/
Pin 12 = o12; /**(Combinatorial, Output feedback output, Active low) **/
Pin 13 = o13; /**(Combinatorial, Output feedback output, Active low) **/
Pin 14 = o14; /**(Registered, Output feedback registered, Active low) **/
Pin 15 = o15; /**(Registered, Output feedback registered, Active low) **/
Pin 16 = o16; /**(Registered, Output feedback registered, Active low) **/
Pin 17 = o17; /**(Registered, Output feedback registered, Active low) **/
Pin 18 = o18; /**(Combinatorial, Output feedback output, Active low) **/
Pin 19 = o19; /**(Combinatorial, Output feedback output, Active low) **/

/** Equations **/

!o12 = o13;
o12.oe = vcc;

!o13 = o17 & o18
     # o16 & !o18 & !o19;
o13.oe = vcc;

!o14 .d !i2
      # i2 & !i4 & o14
      # i2 & i4 & !o14;
o14.oe = OE;

!o15 .d !i2
      # i2 & !i4 & !i5 & !o14 & o15
      # i2 & !i4 & i5 & o14 & o15
      # i2 & i4 & !i5 & o14 & o15
      # i2 & i4 & !o14 & !o15
      # i2 & i5 & !o14 & !o15
      # i2 & !i4 & !i5 & o14 & !o15
      # i2 & i4 & i5 & o14 & !o15;
o15.oe = OE;

!o16 .d !i2
      # i2 & !i5 & o15 & o16
      # i2 & !i4 & !i5 & o14 & o16
      # i2 & i5 & !o16
      # i2 & i4 & !o15 & !o16
      # i2 & !o14 & !o15 & !o16;
o16.oe = OE;

!o17 .d !i2
      # i2 & !i3 & i6 & o17
      # i2 & !i3 & o17
      # i2 & !i5 & i6 & o17 & !o19
      # i2 & i3 & i5 & !o17
      # i2 & i3 & !i6 & !o17
      # i2 & i3 & !o17 & o19
      # i2 & !i6 & !o17 & o19;
o17.oe = OE;

!o18 = i3 & o17
     # !i3 & !o17 & o19;
 

!o19 = !i4 & o15 & o16
     # !i4 & o14 & o16;
 

--- End code ---

You can see four outputs are registered so there is a clock and a output enable

Bassman59:

--- Quote from: caius on July 28, 2021, 08:13:30 pm ---
--- Quote from: Bassman59 on July 28, 2021, 07:40:02 pm ---

I suppose you should learn how to design sequential circuits in Verilog.

--- End quote ---

Yes, obviously.But, as said,implementing a PLD with combinatorial logics is easy.Here's an example :
--- End quote ---

implementing that combinatorial logic in Verilog or VHDL is similarly trivial.

My point is that you have to learn the language before you can port the code to it.

Once you do -- and the stuff you need to know will take you a day to learn -- you'll see that you can very easily do what you ask.

caius:
If I had time I would gladly learn Verilog but sadly too many things to do in real life.That's why I asked for help here  :D

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