Implementing Verilog designs in real hardware

[agehall]

So I consider myself a newbie when it comes to HDL but I get by. I’ve done a few small designs that I’ve implemented in CPLDs before but only fairly basic stuff and most HDL things I’ve done so far have only been simulated.

I’m now trying to step up my game a little and I’m glancing at all the different things that Xilinx provides, like IOBUFs and other things. Do I need to care about them or is Vivado typically smart enough to do-the-right-thing(tm) if I just hook up my design to external pins? And if I should manually add these things and other elements available instead of letting the tools infer them, is there a good place to start reading about how to use these?

I know these questions are kind of vague but I need some guidance. I’m at the point where I think I need to ask some questions but not 100% sure what the questions should be. Any pointers are appreciated.

[mblinov]

Specifically for I/O pins, Vivado should figure it out just fine.
Vivado can infer many (but not all) primitives from the way in which the verilog is written - Xilinx document some of this under chapter 4, called "HDL Coding Techniques" of the manual here:

https://docs.xilinx.com/v/u/en-US/ug901-vivado-synthesis

However sometimes you really want to instantiate a concrete primitive in order to have full control over its presence and name - I used to do this with BRAM blocks, because I wanted to have consistent RAM layout and naming in order to then initialize those blocks with data using TCL in post-layout, without having to re-do the synth/PnR step. For this, Xilinx provide a guide here:

https://docs.xilinx.com/r/en-US/ug953-vivado-7series-libraries

You probably want to look under the chapter "Design Elements"

[asmi]

It will infer basic IO buffers on it's own (stuff like IBUF/OBUF/IOBUF), but if you want to use advanced IO features (like DDR, SERDES), you will need to instantiate them manually in your HDL.

[agehall]

Thanks guys! That’s exactly what I needed to hear!

I have a project that I’m working on that will be far bigger than anything else I’ve done in HDL so far and I guess I’ll just push on without much concern at the moment and tackle issues as I run into them!