In Verilog, is it possible to define XXX only if a parameter is set?

[BrianHG]

In Verilog, is it possible to define XXX only if a parameter is set?

I have a bunch of portions of my code where I include or exclude using `ifdef XXXX, `else XXXX, endif.

However, instead of globally `define XXXX, for each instance of my module, I wish for that `define to be turned on or off based on a parameter.  Is there a way to do this?

[cruff]

Not sure what you need to accomplish, but can you just use a regular parameter and use if statements within a generate block and test for parameter equal to zero or not?

[BrianHG]

That will only work for code I have inside the 'generate' & 'endgenerate'.
I have too may little snipets of code all over the place which are either there or not there depending on the option of the `define.
I'll stick with the good old `define for now unless I want to re-engineer the code.

My other choice is to have 2 version of the module, 1 with the enhanced features, one with the vanilla layer.

[langwadt]

That will only work for code I have inside the 'generate' & 'endgenerate'.
I have too may little snipets of code all over the place which are either there or not there depending on the option of the `define.
I'll stick with the good old `define for now unless I want to re-engineer the code.

My other choice is to have 2 version of the module, 1 with the enhanced features, one with the vanilla layer.

make a file that contains `define XXXX use generate and param to conditionally include that file where you need it?

[Bassman59]

My other choice is to have 2 version of the module, 1 with the enhanced features, one with the vanilla layer.

With VHDL, you could create two (or more) architectures for one entity, and select which one is used with a generic or a configuration. Just sayin'.