Incrementing a counter in Verilog

[Miti]

Looking through code examples in Verilog I found multiple ways to increment a counter and I wonder if there's any difference.

Code: [Select]

reg [19:0] counter;

// Method 1
if (condition) counter <= counter + 1'b1;

// Method 2
if (condition) counter <= counter + 20'b1;

// Method 3
if (condition) counter <= counter + 20'd1;

// Method 4
if (condition) counter <= counter + 1;

All seem to work but what are the dangers?

Cheers,
Miti

[asmi]

They are equivalent, and will infer the same logic. The only thing is some synthesizers will issue a warning for the last method to the effect of "truncating number", as they treat dimensionless numbers as 32 bit values, and so it will need to chop off higher bits.

[Miti]

Thanks asmi!