Author Topic: inout with physical pins in Verilog  (Read 3046 times)

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Offline ivan747Topic starter

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inout with physical pins in Verilog
« on: October 18, 2023, 09:10:40 pm »
Hi everyone,

I am on Quartus Prime and assigned a pin to a inout in the assignment editor. Just to be 100% sure (I don't want to fry my dev board):

When I set this inout to 1'bz is the pin automatically setup as an input?

For microcontrollers you normally have two separate registers: one for pin direction and one for the output value when the direction is set to output. But on FPGAs it looks like there is no separate register controlling direction (in the code). This is why I ask.
 

Offline ataradov

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Re: inout with physical pins in Verilog
« Reply #1 on: October 18, 2023, 09:28:14 pm »
Yes, and you have the same semantics as in the MCUs. Typically if you want the pin to be bidirectional,you would do something like
Code: [Select]
assign io_pin = oe_w ? value : 1'bz;
The pin is always available as an input, you are just enabling or disabling the output driver and setting the driven level.

Also, some FPGA tools do require separate explicit control for the direction. Efinix  is one example for this.
« Last Edit: October 18, 2023, 09:30:48 pm by ataradov »
Alex
 

Online langwadt

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Re: inout with physical pins in Verilog
« Reply #2 on: October 18, 2023, 09:30:46 pm »
Hi everyone,

I am on Quartus Prime and assigned a pin to a inout in the assignment editor. Just to be 100% sure (I don't want to fry my dev board):

When I set this inout to 1'bz is the pin automatically setup as an input?

For microcontrollers you normally have two separate registers: one for pin direction and one for the output value when the direction is set to output. But on FPGAs it looks like there is no separate register controlling direction (in the code). This is why I ask.

yes an inout pin assigned Z will be input, the alternative is manually instatiating a tristate output buffer and then control the tristate enable


 

Offline asmi

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Re: inout with physical pins in Verilog
« Reply #3 on: October 18, 2023, 10:36:22 pm »
Most tools will instantiate an IO buffer automatically once they see instruction like the one provided by ataradov, but if you need more control over the buffer (for example enabling/disabling ODT if it's available), you will need to manually instantiate the corresponding primitive. These are usually described in detail in documentation for your FPGA family.
 
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Offline ivan747Topic starter

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Re: inout with physical pins in Verilog
« Reply #4 on: October 24, 2023, 12:01:28 am »
Thank you everyone. I can confirm the IO is working as expected, no damage.
 


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