input [7:0] data; in verilog. Serial or parallel?

[Dmeads]

Hello!

im messing around in verilog, and i have an 8 bit input data variable of type wire.

does this mean that the data will come into the module one bit at a time? or do all the bits come in parallel and the one wire acts as 8?

thanks!

[hamster_nz]

8 bits in parallel.

[mrflibble]

This one might be useful for a quick lookup of verilog related questions:
http://www.asic-world.com/verilog/veritut.html

[SethGI]

In verilog, when you use the [n:m] syntax, you're specifying a bus. That means, as others have answered, it'll come in in parallel. So 8 wires.

The most important thing everyone needs to know about verilog is it is NOT a programming language (at least how you'd typically think about it). You're not specifying what the FPGA should *do*, you're specifying how to connect the hardware. Even things like case switches which feel more like imperative programming are really just convenient ways to specify the hardware connections. In that context, it wouldn't make much sense for the 8 bits to somehow serialize themselves, you'd have to specify the hardware for that. Go ahead and look at the visualization tools in your compiler each time you compile to understand the hardware you're implying. I think the biggest thing which causes people issues in FPGA programming is they think "what are the steps I need to take to get the desired behavior" and try to program in those steps, whereas  the correct question is "what hardware do I need for the desired behavior". Sorry for the tangential rant you likely already (kinda) understood, but this is really important to keep in mind when learning verilog.