Electronics > FPGA

Input signal synchronization

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zer0c00l:
I have a design that takes CLK A. Within this design there is a sub-block which takes CLK B. The design has a clock divider which takes CLK A and divides it by half to give CLK B which is used by the sub-block. Now I want to synchronize an external signal (coming from outside of the design) and use it in my sub-block. It won't be used in CLK A domain, and only be used in CLK B domain. Can I synchronize this external signal with a standard 2FF synchronizer in CLK A domain and just use it in CLK B domain since CLK B domain is derived from CLK A. The signal itself is relatively slow even from CLK B perspective.




In the above approach is the input signal still considered synchronized from the perspective of CLK B since CLK B is derived from CLK A

hamster_nz:
The signals may be synchronized enough for this deisgn to work reliably.

You would need to use your tools to perform static timing analysis to confirm it is - if the relative phase of the two clocks is not favorable you may still get timing violations.

If you just use FFs to divide your clock you may not get a valid derived clock constraints, and Static Timing Analysis may fail to check it properly.

You will need to look very closely at the timing report to be sure it is accurate.

KrudyZ:
If CLKB is just one half of CLKA then I would create a clock enable line for the sub-block using a simple toggle flip flop and run everything off CLKA.

SiliconWizard:
The question is, why not synchronize with CLK B directly? Probably something we are missing here.

Otherwise, you'd need to tell us what the clock divider is exactly. Is it using a dedicated clock divide resource with a guaranteed phase relationship with CLK A? Is it written in pure HDL?


nctnico:
I wouldn't implement the circuit this way on an FPGA assuming the clock divider is implemented using regular FPGA logic. The delay from clock A to B is unknown. It is also possible the clock B contains false edges due to variations in LUT  and interna delay timing.

A better way is to synchronise all internal logic to clock A.

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