I/O Standards on an FPGA

[steamedhams]

I am currently looking at the dynamic power usage of an FPGA and I have started to look into the different I/Os offered.
I have read the datasheets and white papers supplied by the major vendors.

When I change an I/O to a different standard, for instance, LVCMOS 1.8V to 2.5V, what is changing internally?
The impedance is controllable? The reference changes?? 

[radiolistener]

When I change an I/O to a different standard, for instance, LVCMOS 1.8V to 2.5V, what is changing internally?

As I know, there is no change in hardware. These settings just affects synthesis, fitting and routing during compilation. Such setting will be taken into account for delay and timing optimizations. Because different I/O standard means different load and different source current and result it affect transition timings.

Such setting doesn't affect reference voltage, doesn't affect impedance or some other hardware change. It just affect timing optimization for a compilation/synthesis process.

But this is just my findings, I'm not sure if that is 100% correct.

[langwadt]

I am currently looking at the dynamic power usage of an FPGA and I have started to look into the different I/Os offered.
I have read the datasheets and white papers supplied by the major vendors.

When I change an I/O to a different standard, for instance, LVCMOS 1.8V to 2.5V, what is changing internally?
The impedance is controllable? The reference changes??

the voltage doesn't change, you do that by connecting a different supply. But the tools configure the output and report timing assuming you connect what you said you did. an IO configured as 1.8V LVCMOS will work just the same with a 2.5V supply. it just might not be exactly to spec

in the case of internal termination resistors they might not have the correct values if you connect a different voltage, and with some IO standards the output might turn of to protect the transistors if you connect a higher than supported voltage


 

[NorthGuy]

I think Xilinx uses different LVCMOS buffers for low (1.8 or less) and high voltages. At least there are bits in the bitstream which change with voltage and there's a configuration pin which sets the voltage for other configuration pins.