Xilinx DCM/PLL phase noise

[NiHaoMike]

I have a Spartan 6 LX100-3 board with an onboard 125MHz clock and I'm trying to get a 36.864MHz clock to drive an ADC.

Initially, I tried this:

Code: [Select]

DCM_CLKGEN #(
.CLKFX_DIVIDE (125),
.CLKFX_MULTIPLY (192),
.CLKIN_PERIOD(8)
) DCM0 (
.CLKFX(dcm0_clkfx), // 192MHz
.CLKFX180(),
.CLKFXDV(),
.LOCKED(dcm0_lckd),
.PROGCLK(),
.PROGDATA(),
.PROGDONE(),
.PROGEN(),
.STATUS(dcm0_status),
.CLKIN(osc_clk),
.FREEZEDCM(1'b0),
.RST(dcm0_status[2] && ~dcm0_lckd)
);
PLL_BASE # (
.BANDWIDTH("HIGH"),
.CLKIN_PERIOD(5.208),
.CLKFBOUT_MULT(24),
.CLKOUT0_DIVIDE(25),
.COMPENSATION("DCM2PLL"),
.DIVCLK_DIVIDE(5)
) PLL0 ( //921.6MHz
.CLKFBOUT(pll0_clkfb),
.CLKOUT0(sys_clk_36p8), //36.864MHz
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(pll0_lckd),
.CLKFBIN(pll0_clkfb),
.CLKIN(dcm0_clkfx),
.RST(~dcm0_lckd)
);It worked but with a lot of phase noise according to my RTL-SDR. (RTL-SDR connected via a 100k resistor as an attenuator.)

The clocking wizard suggests this:

Code: [Select]

PLL_BASE # (
.BANDWIDTH("HIGH"),
.CLKIN_PERIOD(8),
.CLKFBOUT_MULT(23),
.CLKOUT0_DIVIDE(26),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(3)
) PLL0 (
.CLKFBOUT(pll0_clkfb),
.CLKOUT0(sys_clk_36p8),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(pll0_lckd),
.CLKFBIN(pll0_clkfb),
.CLKIN(osc_clk),
.RST(1'b0)
);Much less phase noise, but the frequency is not exact.

Am I correct that the DCM is inherently noisy or did I have it configured to use spread spectrum by mistake? Is there any way to get an exact 36.864MHz clock (to within the frequency accuracy as the 125MHz master clock) and have low phase noise using only the clocking resources on the FPGA?

[BrianHG]

This '36.864MHz' is a nasty factor.
If this is your system crucial frequency, then you need a standard off the shelf 12.288MHz oscillator.
That will make you a clean 36.864MHz, or, best go with an exact 38.864MHz oscillator.
Now, your 125MHz wont be exact...

[Bassman59]

This '36.864MHz' is a nasty factor.
If this is your system crucial frequency, then you need a standard off the shelf 12.288MHz oscillator.
That will make you a clean 36.864MHz, or, best go with an exact 38.864MHz oscillator.
Now, your 125MHz wont be exact...

Or design the board to use both, and manage the clock domain crossings in the usual manner.

[Someone]

Am I correct that the DCM is inherently noisy

Yes.

The estimated jitter from the IP configurator is accurate (and focused on peak to peak deviations) so you can play around with configurations there to find the best design. With a lowest common multiple of 576GHz its going to need a few stages to avoid fractional steps with their added noise. There are simple prime factor solutions of 3 PLL stages (or 2 from a 8/16/32 MHz clock).

[asmi]

Few years ago I bought this kit: https://www.sitime.com/time-machine-oscillator-programmer and since that I never had any problems finding oscillators with whatever frequency, and, more importantly, didn't have to stock a whole bunch of different part numbers for different frequencies. It can program a whole bunch of different oscillators from simple 4 pin ones all the way to super-TCXOs and ultra-low jitter differential oscillators and VCXOs. For most parts, it supports frequencies with precision down to a single Hz, so things like 32.987654 MHz are absolutely possible.
So if you frequently find yourself needing oscillators with all kinds of frequencies, you might want to invest into this kit. It's a bit on a pricey side, but convenience it brings is unmatched. The kit also comes with a few sample blank devices to get you started (mine came with SiT2018BA-S1, SiT8008BI-11, SiT9121AI-1B1 and SiT9121AI-2C1, 3 devices each).
I believe Microchip also has it's own version of that system.

[BrianHG]

Uh, ok, if you want a super high quality VCXO with 2 PLL and 6 programmable outputs from 1 regular crystal, use TI's CDCE925.  Flash programmable and in system realtime frequency tuning.

Analog voltage tuning VCXO input pin as well as I2C software internal dac drive on that pin to tune the crystal.  Preprogrammable with more than 1 optional setup controlled by 1 or 2 inputs.

Dirt cheap version CDCE913 - 1 pll 3 outputs.  @2.58 each + 25cent xtal, costs less than a high quality crystal oscillator.

Up to 160MHz out with an 8-32MHz crystal.
Spread spectrum support.

[asmi]

Uh, ok, if you want a super high quality VCXO with 2 PLL and 6 programmable outputs from 1 regular crystal, use TI's CDCE925.  Flash programmable and in system realtime frequency tuning.

Analog voltage tuning VCXO input pin as well as I2C software internal dac drive on that pin to tune the crystal.  Preprogrammable with more than 1 optional setup controlled by 1 or 2 inputs.

Dirt cheap version CDCE913 - 1 pll 3 outputs.  @2.58 each + 25cent xtal, costs less than a high quality crystal oscillator.

Up to 160MHz out with an 8-32MHz crystal.
Spread spectrum support.

That is massive overkill. A single small part with custom frequency, on the other hand, is simple and easy. SiT8008B FP devices go for about $1-2 per device depending on volume, and you can program any frequency from 1 to 110 MHz with a step of 1 Hz.

[miken]

Chaining Xilinx clock elements makes the final jitter considerably worse, in my experience. You could try setting the bandwidth to LOW but I imagine it won't help that much.

In an ideal world you wouldn't clock an ADC with an FPGA-generated clock, no matter the number of stages, but it all depends on what your target performance is.

[BrianHG]

I've use the aforementioned single TI PLL with 1 output dedicated for ADC, 1 for DAC, 1 and for FPGA clk input, each with their own set clk & divider.

[radiolistener]

it's better to feed ADC directly from ultra low phase noise oscillator. Because FPGA logic has significant jitter, it will reduce ADC dynamic range.