Electronics > FPGA

JESD204B over fiber

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schildch:
Hello everyone,

I have a project, were I have a high speed ADC with a JESD204B interface in a remote location (tens of meters away). I am currently considering connecting the ADC to the main processing platform over an optical fiber. Does anybody have some experience with the reliability/stability of JESD204B over fiber? Or any general tips e.g. selection of transceiver, clocking, …?

fourtytwo42:
2 second search gets https://www.ti.com/lit/an/slyt663/slyt663.pdf and there are plenty more.

ejeffrey:
#1 question is do you need determenistic latency/phase alignment of multiple ADCs needed?  If so you need to use subclass 1 w/ SYSREF.  If not and subclass 0 is sufficient then it should be easy: you basically just wire it up and go.  The application note linked above talks about how to distribute clock and SYSREF in a multi-converter setup.

What are your sample rate / bit depth / channel count needs?  JESD204b is limited to 12.5 Gb/s with a 10 Gb/s effective data rate from 8b10b encoding.  Depending on your needs you might at least look for a JESD204c converter that can operate at a higher data rate, allowing you to get by with fewer lanes (and fewer fibers).  ~28 Gb/s optical modules are fairly common since they are used for 25/100 Gb/s ethernet.

tchiwam:
I am getting a kit of SFP+ today for similar purpose. My plan is to bring the clk and pps back to the sender to 0 skew the remote clk distribution.

For me it is to keep the time reference on a solid platform while the receivers are going to move around.

glenenglish:
I have done this
I sent clock out to the ADC board, and used a PLL out there to clean up the jitter of the link clock.
because we all know clean clocks are the secret to sampling happiness.

I also sent sync control on fibre (clocked by the source clock)  , and also the SPI control of the converters - I multiplexed them onto one strand and used a small FPGA at the ADC end to demux the signals.

-glen

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