Hi! I'm working on a broken oscilloscope implemented as a Kintex XC7K325T connected over PCIe to an Intel PC. The FPGA used to show up on the PCIe bus and then one day it stopped, shortly (but not immediately) after I disassembled and reassembled the scope to grab EEPROM. Here's what I know:
- Power buses are ok - there are many, this was a pain to validate but so it goes.
- Bitstream loads. INIT_B, DONE, and PROG_B are all high (yellow, green, yellow LEDs).
- Checksum passes. (rto2044-jtag.txt)
- Early SPI bus tasks are completed by FPGA (3x ADF4360 VCO/PLLs program and lock - green, green, green LEDs)
- SYS_PWROK and PLTRST# go high (inputs from system to FPGA)
- PCIe REFCLK appears (input to FPGA) but heavily distorted. I actually have a before/after on this one. Distortion is consistent with an open circuit at FPGA, not a short, not a decoupling capacitor or connector issue.
- REFCLK (capacitively coupled) has a common mode voltage of 8mV (measured) instead of 800mV (expected) at FPGA.
There are two things I would appreciate advice on from people wiser in the ways of FPGAs (my own experience is very elementary):
- From REFCLK_diagram.png and IBUFDS_GTE2.png it sure looks like the termination settings come from the bitstream rather than an enable line from the fabric. Since I know that MGTAVCC is up and the bitstream is loaded, I would expect this to enable termination, but it doesn't. Vcm is 8mV, not 800mV. I am likely missing something, but I don't know what. Any ideas?
- I don't see any debug interfaces for the Multi Gigabit Transceivers in the Vivado JTAG tool. Evidently they weren't baked into the design. Is there any other way to get a status out of the MGTs or PCIe IP?
I'm about ready to throw in the towel on this -- I can order a replacement, it just means admitting defeat, but I'm still down for pulling on another thread or two if someone can point me in a possible direction. Thanks in advance!