Best approach to drive several ADCs with a Xilinx Zynq 7010

[arijav]

Hello,

I am looking for some advice from experienced Zynq users. I need to gather signals from up to 32 single channel ADCs (24bit with SPI Iface) and send them over ethernet. The sampling rate could get up to 1MSPS per ADC and the signals need to be fully synchronized among the ADCs. I wanted to let the PL part of the Xilinx do the hard job of the parallel acquisitions and preparation of the data packages for the PS part to take over and send them over UDP.

What is the best approach to do it? Shall I create a custom Verilog block in Vivado that configures the ADCs via SPI, gathers the signals, prepares the whole data packages and connect it to the Processing System through an AXI DMA block with FIFO or is there an easier way to do this via standard IP blocks in Vivado? Any other suggestion?

The Ethernet part is already working fine, I have integrated FreeRTOS+TCP due to good experiences that I've had in the past with a STM32H7. My current question relates just to the acquisition part.

Thanks in advance

[glenenglish]

Use the 'generate' keyword inside HDL to make light work of replicated blocks

turn the 32 ADCs into a single 24 bit wide AXI 32-TDM stream , with will enable efficient use of any processing or filtering between the adc and the ZYNQ.

Use a AXI-S FIFO to interface to the PS, and choose interrupt levels and FIFO depth  appropriately as required to satisfy designed overall system latency and RTOS response time.  DMA into locked cahce lines, or OCM, or DDR whatever required.......

clock , CS and likely SDI can be common for all devices, but given the load of 32 of them, split into at least say sets of 4 or 8 per set
if you have the IO, you could run each device with its own set of wires. all timed of course and constrained as required to the pins in vivado. you'll find its sensible to group signals though, and resets. if the ADCs  have resets use them. its likely you'll be able to send the same data to the ADCs so single SDO (again, group into say 4 or 8  to reduce bus load ) will be common, as will CS. SDI will be one for each of course. if the ADC has a sample input, use that of course. 1 Msps on 24 bits is only 24 MHz + a bit spi clock, which is slow.......

You must time everything - In Vivado, be sure to time every signal. If you do not, it will fight you all the way.
opposite to the old ISE days.
No global async resets !, use local retimed synchronous resets from global resets

[tom66]

I think glen's solution is the best if you want to get stuck in and write some proper HDL.

However there may be a "lazy alternative", which is to use many Xilinx AXI Quad-SPI blocks.  Each to be set as a single SPI channel.

The challenge will be time synchronising the captures but if you have the same master clock for all the devices and use a simultaneous write (connect the SIN/CS of the ADC's to one master) then you can read the samples back 'at leisure' inside each IRQ.

Your CPU would be busy handling the IRQs from the SPIs but it may be possible to use DMA and the internal buffer of the SPI FIFOs to spread this out so the CPU isn't kept too busy.  Potentially the Zynq could be set up so one core acquires data and the other processes it, or you could use an RTOS to manage that.  I think it could be a little trickier to do it in Linux given the real time nature.

[glenenglish]

I like Tom's answer !

yes drop a whole load of AXI quad spi blocks. should be easy enough to control reset of those blocks, so they stay deterministically together and fan out a single CS to all ADCs if necessary .
QSPI FIFO can be pretty deep, and you *could* add AXI stream fifos and then an AXI stream combiner........ just as long as start up etc is all sync and determ.

sorry I got all complex again. LOL.

or you can drive CONVERT if there is such a signal on the ADC.
What is the ADC ?