lattice batch compilation

[fabiodl]

I need to batch compile a project composed of multiple verilog files.
For simplicity,assume there is a top module in file top.v instantiatian sub (declared in sub.v).
ispflow does not allow to specify multiple files. If the -i option is specified multiple times the following error id given:

Error: Input File already entered

Conversely, if only the top module file is specified, Synopsys Verilog Compiler fails with the following error

Reference to undefined module sub

What is the correct way to do a batch compilation?

[fabiodl]

if someone has the same need, I found out that it is possible to use c:/ispLEVER_Classic2_0/lse/bin/nt/synthesis.exe  to crate ad edf file, and then provide such file to ispflow.
The output jed however missed the usercode, and diamond programmer fails in verifying it. it is necessary to add UH00000000* at the end of the jed file.