Arria 10 FPGA's in china

[ali_asadzadeh]

Hi,
I'm looking into the some newer FPGA's in china, I'm interested in the ones that have the floating point DSP like Arria 10 from Intel, I want to know what cheap part numbers from Arria 10 family can be found in china, I need my Chinese friends help in here, what part numbers are very cheap there, as we have ZYNQ with good prices out there, like this cheap ZYNQ part XC7Z020-2CLG400I

[AndreZheng]

  Arria's price is about x100 comparing to the Xilinx XC7Z020 chip. If you want to switch to Intel SoC, the equivalent chips are Cyclone V SoC e.g. 5CSEBA2. The retail price is around 20$.

[OwO]

Xilinx chips are more common than Intel/Altera ones here, and are usually priced lower for similar specs. It is very uncommon to do floating point math in an FPGA, and even when you have to handle floating point, it's more common to first convert to fixed point (and make note of the scale), process it, then convert back to floating point. The Xilinx FFT core does this for example.

[ali_asadzadeh]

Thanks for the feedback,
I have found a link,
Can you check it to see if they are ok?
https://detail.1688.com/offer/562103433297.html?spm=a26352.13672862.offerlist.5.4b9e1e62mW4dAI

The Arria 10 looks very interesting, if the above price and parts are ok

[OwO]

If you read the description you'll see the list price is fictitious and you have to message the seller for the price. I did a quick search and no one actually sells Arria 10 chips here (they are all automated listings probably copied from digikey).

[BrianHG]

The '10AX016C4U19E3SG' is 319$ new from Mouser or Intel.  At that price, I would just buy the original.

All FPGAs can do floating point, even a Cyclone IV, it's just the maximum FMAX and the pipeline clock length.

Tha Arria gives you the really fast DDR3/4 speeds, PCIx and high speed serdes, plus that 10megabit core block ram and 160k logic gates.

[BrianHG]

Also, there are 2 types of floating point units available.  1 is the NIOS unit which has all the functions embedded and is designed for all functions in 1 unit meant to run with the NIOS core.

There is also the basic ALTFP_MULT/ADD function which allows super pipelining of floating point which can hit the FPGA core FMAX and continuously stream mults/adds every clock cycle, just like any Verilog multiply/add function.

[filssavi]

The '10AX016C4U19E3SG' is 319$ new from Mouser or Intel.  At that price, I would just buy the original.

All FPGAs can do floating point, even a Cyclone IV, it's just the maximum FMAX and the pipeline clock length.

Tha Arria gives you the really fast DDR3/4 speeds, PCIx and high speed serdes, plus that 10megabit core block ram and 160k logic gates.

Of course arria can do floating point, all FPGAs  now can do floating point.

The fact that they can however does not mean you should...
It will take a huge amount of logic, run slow as hell, and burn a ton of power when compared to a simple fixed point calculation

Now I can understand that fixed point can be a little mind-bendy at times but it is not that complex after all

[BrianHG]

The '10AX016C4U19E3SG' is 319$ new from Mouser or Intel.  At that price, I would just buy the original.

All FPGAs can do floating point, even a Cyclone IV, it's just the maximum FMAX and the pipeline clock length.

Tha Arria gives you the really fast DDR3/4 speeds, PCIx and high speed serdes, plus that 10megabit core block ram and 160k logic gates.

Of course arria can do floating point, all FPGAs  now can do floating point.

The fact that they can however does not mean you should...
It will take a huge amount of logic, run slow as hell, and burn a ton of power when compared to a simple fixed point calculation

Now I can understand that fixed point can be a little mind-bendy at times but it is not that complex after all

Citations needed.  I read Altera/Intel's floating point algorithms mega-function catalog.  Your assessment isn't true.

[OwO]

Try instantiating a simple float adder/subtractor, and compare that with a simple signed +. See how many LUTs each uses. The float IP might even use a DSP block.

[BrianHG]

Try instantiating a simple float adder/subtractor, and compare that with a simple signed +. See how many LUTs each uses. The float IP might even use a DSP block.

FP mult/add/sub uses only 4 18bit multiplier blocks, or 1 variable precision DSP block.  The LUT and cells were negligible.

You can place over 150 single precision Floating Point units in the listed Arria and still have room.

It is rated at 140 GFLOPs.

[filssavi]

Well if you go with fixed point you can have at least 4 times (probably more) as many operations with the same usage, now if this is not a lot I don’t know what is

Also taking into consideration the

also I seriously doubt that you can implement standard compliant FP (that means with all normalisations and rounding modes with just 4dsp blocks and negligible LUTs

As for the quoted 150 Gflops you can do more (160) with a multicore Ti DSP (C66) that costs 1/10 of the FPGA, then if you need just sheer throughput in floating point a RTX 2080ti GPUs can hit 11 Teraflops

So unless you are actually forced to do floating points (and you can’t as someone else said you just would convert to fixed point and then go back at the end) doing it on an FPGA would be less than a bright idea

[ali_asadzadeh]

Guy's I know all FPGA's can do Floating point, the point about Arria 10 and newer FPGA's is that it has hardened DSP blocks with Floating point capability, you do not need to implement it with the LUT's and so the Clock for that monster is huge! you can get GFLOPs with them easily

[colorado.rob]

Guy's I know all FPGA's can do Floating point, the point about Arria 10 and newer FPGA's is that it has hardened DSP blocks with Floating point capability, you do not need to implement it with the LUT's and so the Clock for that monster is huge! you can get GFLOPs with them easily

This is the sort of workload that an NVidia Tegra is designed for.  Link a lower cost FPGA, if you need the programmable logic, with a Tegra to do the math crunching.  This is likely to be both less expensive and higher performance at the expense of some latency.

The latest Tegra can do a TFLOP. https://en.wikipedia.org/wiki/Tegra#Xavier

[ali_asadzadeh]

This is the sort of workload that an NVidia Tegra is designed for.  Link a lower cost FPGA, if you need the programmable logic, with a Tegra to do the math crunching.  This is likely to be both less expensive and higher performance at the expense of some latency.

The latest Tegra can do a TFLOP. https://en.wikipedia.org/wiki/Tegra#Xavier

Where can we buy Tegra?Do they sell it to hobbyist and in single QTY?