Author Topic: Xilinx FPGA Drive Strength Explanation  (Read 347 times)

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Offline petersanch

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Xilinx FPGA Drive Strength Explanation
« on: July 30, 2020, 08:41:33 am »
On a hardware level, how does the drive strength of Xilinx FPGAs work? Is a different transistor used when a different drive strength is selected? Is it like a current source?

As an example, if a 6mA drive strength is selected then can a indicator Led connect directly to the FPGA without a series resistor without causing damage?


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Online BrianHG

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Re: Xilinx FPGA Drive Strength Explanation
« Reply #1 on: July 30, 2020, 12:39:05 pm »
You can, but remember, now your series resistance for the LED will be inside the FPGA generating additional heat on the die.
You are much better off using the max current output with an external series resistor.  Now that added heat will be outside the FPGA and you will not be stressing a mosfet on the FPGA silicon which wasn't designed to be forced to a middle voltage value as the LED pulls the voltage up (preferred IE led anode tied to VCCIO and cathode through resistor to IO pin.) or down.
« Last Edit: July 30, 2020, 12:53:46 pm by BrianHG »
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Offline filssavi

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Re: Xilinx FPGA Drive Strength Explanation
« Reply #2 on: July 30, 2020, 01:21:39 pm »
Functionally you are correct, the drive strength is your maximum available current output, however it is typically not used (and I guess designed for) as you would use a discrete current limiter, thus you need to be careful about what you do.

The typical application is to limit the slew rate on digital signals/interfaces for signal integrity reasons, you might not want an I2C bus for example to have a sub nanosecond edge, as it  only complicates your EMI compliance without benefits. A high speed serial communication line on the other end might need all the speed it can get to keep as much margin as possible. In all these applications the limiter circuit is only working for a very small time window (when switching only), thus the thermal and power design for the whole FPGA is done with that in mind

Now in your application you have to keep in mind this last thing, so if you want to use it for some sort of alarm/warning LED that is very rarely on, it might work, if you want to drive directly a bar graph meter (like the audio level meters with 10-12 leds), that might not be the best idea ever

All in all you need to respect the datasheet limits on maximum per pin, per bank and per chip power draw limits, and having an X mA constant load on a single pin might significantly cut into your budget. The same consideration do apply for thermal
 
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Offline Someone

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Re: Xilinx FPGA Drive Strength Explanation
« Reply #3 on: July 31, 2020, 07:59:43 am »
General concept: there are many FETs in the output stage and more/less of them are used with stronger/weaker drive settings.

More specific: the "ma" of the drive setting is not even close to the current available at the pin, check the IV curves in the IBIS files.
 

Offline hamster_nz

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Re: Xilinx FPGA Drive Strength Explanation
« Reply #4 on: July 31, 2020, 11:59:50 am »
When I tested, a low resistance load or short to ground at drive strength X will be supplied significantly more that X current. IIRC when set to 15mA it would source 50mA.

It indicates how much current will be sourced or sunk while still maintaining the specified Voh or Vol (high and low levels for the I/O standard).
« Last Edit: July 31, 2020, 12:01:51 pm by hamster_nz »
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Offline petersanch

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Re: Xilinx FPGA Drive Strength Explanation
« Reply #5 on: August 01, 2020, 08:32:27 am »
Thanks for the explanations all! :-+
 


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