Electronics > FPGA

Lattice Diamond - how to overcome absurd clock routing requirements?

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axemaster:
Hi, I am writing a simple SPI Slave port for a ECP5 FPGA, using Lattice Diamond software.

The SPI port has a "sclk" signal, which is an input. I don't care about the frequency. I plan for 20MHz but really anything down to 1MHz would be fine.

I have already tested on testbench and my design is synthesizable. However, Lattice is insisting that I MUST input "sclk" on a dedicated clock port. Here's the exact error:


--- Code: ---ERROR - USER LOCATE of clock driver 'sclk' at an illegal pin 'V21'. Unable to reach a CIB entry point for general route clock sclk_c in the minimum required distance of 1 PLC.
Please check if the pin is a legal clock pin (e.g. dedicated clock pin, GR pin) by
1) Opening 'Tools->Spreadsheet View' on the top
2) Choosing 'Pin Assgnments' tab in the middle
3) Checking 'Dual Function' column (PCLK*, GR*, etc.) for the pin
--- End code ---

How can I overcome this nonsense? I can't find any options to suppress this restriction. Does this mean that any signal Lattice Diamond infers as a clock will refuse to route unless it's on the "correct pin", even if it's 1Hz signal???

BrianHG:
Can we see the HDL?

Sometimes certain uses or constraints/rules/limitations might need to be observed when using a generic IO pin to clock logic or to be used as a generated clock output.

Also, Lattice seems to prefer (as I have seen in their example designs) that you wire each required IO to their IO primitive as a normal course of action as their compiler/fitter seems to only perform the most basic automatic design IO primitive inference compared to compilers such as Altera's and Xilinx's which will take anything you throw at it.  A hassle, but check how their IO primitive's parameter/ports supports defining an IO feeding their logic's local or global clock net.  Google may help you here with the correct search terms.

BrianHG:
Maybe read here: https://www.eevblog.com/forum/microcontrollers/lattice-diamond-secondary-clock-resources/

SiliconWizard:
You can read the "General Routing for Clocks" section in the "ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide".
It's not very detailed, but explains the issue.

Bassman59:

--- Quote from: BrianHG on May 12, 2022, 07:04:45 pm ---Also, Lattice seems to prefer (as I have seen in their example designs) that you wire each required IO to their IO primitive as a normal course of action as their compiler/fitter seems to only perform the most basic automatic design IO primitive inference compared to compilers such as Altera's and Xilinx's which will take anything you throw at it.

--- End quote ---

With the exception of DDR primitives, I've never instantiated an I/O or clock buffer primitive in a Lattice design.

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